# US 8,541,841 B2 · Semiconductor devices and semiconductor device manufacturing methods

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- Number: US 8,541,841 B2
- Document ID: US8541841B2
- Status: Granted
- Kind: B2
- Application number: 13/412,248
- Filed: 2012-03-05
- Published: 2012-06-28
- Granted: 2013-09-24
- Earliest claimed: 2008-12-01
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Won-joo Kim; Sang-moo Choi; Tae-hee Lee; Yoon-dong Park
- Inventors: Won-joo Kim; Sang-moo Choi; Tae-hee Lee; Yoon-dong Park
- Web page: https://patentgrep.com/patent/US8541841B2

## CPC

- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10D 30/711: {having floating bodies}
- H10D 86/01: Manufacture or treatment
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure.

## Claims

### Claim 1

A semiconductor device including a localized silicon on insulator (SOI) structure, comprising:
a substrate region;
a first well of a first conductive type in the substrate region;
a second well of a second conductive type;
a third well of the second conductive type;
a silicon on insulator (SOI) structure filling a recess in the substrate region above the third well,
wherein the second well and the third well are separated by the first well and are formed in two side regions of the first well so as not to be adjacent to each other, at least one of the second well and the third well are on the first well,
wherein a drain and a source of a first transistor are in the second well, and a drain and a source of a second transistor are in the SOI structure, and
wherein driving circuits include the first transistor, and memory cells include the second transistor.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a bias voltage applied to the second well is different from a bias voltage applied to the third well.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein different bias voltages are applied to the SOI structure in the third well and the driving circuits in the first and second wells.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein different bias voltages are applied to the memory cells and the driving circuits.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the driving circuits are not formed on the SOI structure.