# US 8,541,836 B2 · Recessed access device for a memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,541,836 B2 - Document ID: US8541836B2 - Status: Granted - Kind: B2 - Application number: 13/674,159 - Filed: 2012-11-12 - Published: 2013-03-14 - Granted: 2013-09-24 - Earliest claimed: 2006-11-13 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Kurt D. Beigel; Jigish D. Trivedi; Kevin G. Duesman - Web page: https://patentgrep.com/patent/US8541836B2 ## CPC - H10D 64/027: {by etching at gate locations} - H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess. ## Claims ### Claim 1 A memory device including a recessed access device, the recessed device comprising: a device recess in semiconductor material and that extends to a first depth and includes a gate dielectric formed in the recess; an extended portion of the device recess that extends to a second depth that is greater that the first depth; field oxide positioned within an interior of the device recess that extends inwardly into the interior of the device recess and into the semiconductor material; active regions formed in the semiconductor material that abut the field oxide; and a gate structure positioned in the device recess. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the field oxide has a thickness that is at least two times thickness of the gate dielectric. ### Claim 3 (depends on 1) The memory device of claim 1, further comprising: a storage device coupled to a selected one of the active areas by a via that extends between the storage device and the selected one of the active areas; a via that extends between the other of the active areas configured to couple a bit line of the memory device to the other of the active areas; and a conductive material positioned on the gate structure that couples the gate structure to a word line of the memory device. ### Claim 4 (depends on 3) The memory device of claim 3, wherein the storage device further comprises one of a trench capacitor and a stacked capacitor. ### Claim 5 (depends on 3) The memory device of claim 3, further comprising: first insulation structures positioned on opposing sides of the conductive material positioned on the gate structure. ### Claim 6 (depends on 5) The memory device of claim 5, further comprising: a second insulation structure positioned between the first insulation structures that abuts the conductive material positioned on the gate structure. ### Claim 7 A memory device including a recessed access device, the recessed device comprising: a device recess in semiconductor material; isolation dielectric laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess; a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation dielectric; a gate in the device recess; and a pair of source/drain regions in the semiconductor material against the isolation dielectric on opposing sides of the device recess, one of the pair of source/drain regions extending deeper into the semiconductor material than the other of the source/drain regions. ### Claim 8 (depends on 7) The memory device of claim 7 wherein the isolation dielectric is laterally thicker than the gate oxide. ### Claim 9 (depends on 7) The memory device of claim 7 wherein the one and the other source/drain regions are of different conductivity. ### Claim 10 (depends on 9) The memory device of claim 9 further comprising a storage device electrically coupled to the lower conductivity of the one and the other source/drain regions. ### Claim 11 A memory device including a recessed access device, the recessed device comprising: a device recess in semiconductor material; isolation dielectric laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess; a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation dielectric; a gate in the device recess; and a pair of source/drain regions in the semiconductor material against the isolation dielectric on opposing sides of the device recess, one of the pair of source/drain regions being of higher conductivity than the other of the source/drain regions. ### Claim 12 (depends on 11) The memory device of claim 11 further comprising a storage device electrically coupled to the lower conductivity of the one and the other source/drain regions. ### Claim 13 (depends on 11) The memory device of claim 11 further comprising a bit line electrically coupled to the higher conductivity of the one and the other source/drain regions. ### Claim 14 A memory cell comprising: a recessed access device comprising: a device recess in semiconductor material; isolation dielectric laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess; a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation dielectric; a gate in the device recess; and a pair of source/drain regions in the semiconductor material against the isolation dielectric on opposing sides of the device recess; a word line electrically coupled to the gate; and a pair of isolation structures laterally over opposing sides of the word line, the isolation structures respectively having an elevationally innermost surface, each elevationally innermost surface of the isolation structures being against an elevationally outermost surface of that portion of conductive material of the gate that is within the device recess. ### Claim 15 (depends on 14) The memory device of claim 14 wherein the elevationally innermost surfaces of the isolation structures are respectively planar. ### Claim 16 (depends on 14) The memory device of claim 14 wherein each elevationally innermost surface of the isolation structures is against an elevationally outermost surface of a respective one of the pair of source/drain regions. ### Claim 17 (depends on 14) The memory device of claim 14 wherein the isolation structures have a respective elevationally outermost portion that is narrower than a respective elevationally innermost portion. ### Claim 18 A memory cell comprising: a recessed access device comprising: a device recess in semiconductor material; isolation dielectric laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess; a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation dielectric; a gate in the device recess; and a pair of source/drain regions in the semiconductor material against the isolation dielectric on opposing sides of the device recess; a word line electrically coupled to the gate; and a pair of isolation structures laterally over opposing sides of the word line, the isolation structures respectively having an elevationally innermost surface, each elevationally innermost surface of the isolation structures being against an elevationally outermost surface of a respective one of the pair of source/drain regions. ### Claim 19 (depends on 18) The memory device of claim 18 wherein the isolation structures have a respective elevationally outermost portion that is narrower than a respective elevationally innermost portion. ### Claim 20 A memory device including a recessed access device, the recessed device comprising: a device recess in semiconductor material; isolation oxide laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess; a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation oxide, the isolation oxide being laterally thicker than the gate dielectric; a gate in the device recess; and a pair of source/drain regions in the semiconductor material against the isolation oxide on opposing sides of the device recess. ### Claim 21 A memory device including a recessed access device, the recessed device comprising: a device recess in semiconductor material; isolation dielectric laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess; a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation dielectric, the isolation dielectric being laterally thicker than the gate dielectric, the isolation dielectric and the gate dielectric being of the same composition relative one another; a gate in the device recess; and a pair of source/drain regions in the semiconductor material against the isolation dielectric on opposing sides of the device recess. ### Claim 22 (depends on 21) The memory device of claim 21 wherein the composition comprises silicon dioxide. ### Claim 23 A plurality of memory cells at least some of which comprise: a substrate comprising semiconductor material; and a recessed access device formed within the semiconductor material, the recessed access device comprising: a device recess in the semiconductor material; isolation oxide laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess; a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation oxide, the isolation oxide being laterally thicker than the gate dielectric; a gate in the device recess; and a pair of source/drain regions in the semiconductor material against the isolation oxide on opposing sides of the device recess. ### Claim 24 A plurality of memory cells at least some of which comprise: a substrate comprising semiconductor material; and a recessed access device formed within the semiconductor material, the recessed access device comprising: a device recess in the semiconductor material; isolation dielectric laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess; a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation oxide, the isolation dielectric oxide being laterally thicker than the gate dielectric, the isolation dielectric and the gate dielectric being of the same composition relative one another; a gate in the device recess; and a pair of source/drain regions in the semiconductor material against the isolation oxide on opposing sides of the device recess.