# US 8,541,835 B2 · Schottky FET fabricated with gate last process

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- Number: US 8,541,835 B2
- Document ID: US8541835B2
- Status: Granted
- Kind: B2
- Application number: 13/571,429
- Filed: 2012-08-10
- Published: 2012-11-29
- Granted: 2013-09-24
- Earliest claimed: 2010-07-12
- Assignees: International Business Machines Corporation
- Applicants: Jin Cai; Dechao Guo; Marwan H. Khater; Christian Lavoie; Zhen Zhang
- Inventors: Jin Cai; Dechao Guo; Marwan H. Khater; Christian Lavoie; Zhen Zhang
- Web page: https://patentgrep.com/patent/US8541835B2

## CPC

- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/6737: {characterised by the electrode materials}
- H10D 30/6743: {Silicon}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/027: {by etching at gate locations}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A field effect transistor (FET) includes a semiconductor on insulator substrate, the substrate comprising a top semiconductor layer; source and drain regions located in the top semiconductor layer; a channel region located in the top semiconductor layer between the source region and the drain region, the channel region having a thickness that is less than a thickness of the source and drain regions; a gate located over the channel region; and a supporting material located over the source and drain regions adjacent to the gate.

## Claims

### Claim 1

A field effect transistor (FET), comprising:
a semiconductor on insulator substrate, the substrate comprising a top semiconductor layer;
source and drain regions comprising silicide located in the top semiconductor layer;
a channel region located in the top semiconductor layer between the source region and the drain region, the channel region having a thickness that is less than a thickness of the source and drain regions, wherein the channel region is in direct contact with the silicide of the source and drain regions;
a gate located over the channel region;
a supporting material comprising oxide located over the source and drain regions on both sides of the gate; and
gate spacers comprising nitride located on both sides of the gate adjacent to the supporting material, wherein the gate spacers are located on top of and in direct contact with the channel region, and wherein the gate spacers are in direct contact with the silicide of the source and drain regions above the channel region.

### Claim 2 (depends on 1)

The FET of claim 1, wherein the semiconductor on insulator substrate comprises an insulator layer underneath the top semiconductor layer, and a bottom semiconductor layer under the insulator layer.

### Claim 3 (depends on 1)

The FET of claim 1, wherein the gate comprises a gate dielectric layer formed over and in direct contact with the gate spacers and the channel region, and a gate metal layer formed over the gate dielectric layer.

### Claim 4 (depends on 3)

The FET of claim 3, wherein the gate dielectric layer comprises a high k dielectric material.

### Claim 5 (depends on 1)

The FET of claim 1, wherein the channel region is from about 0 nanometers thick to about 7 nanometers thick.

### Claim 6 (depends on 1)

The FET of claim 1, wherein the source and drain regions are from about 10 nanometers thick to about 20 nanometers thick.

### Claim 7 (depends on 1)

The FET of claim 1, wherein the supporting material is located on top of and in direct contact with the silicide of the source and drain regions.