# US 8,541,831 B2 · Nonvolatile memory device and method for fabricating the same

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- Number: US 8,541,831 B2
- Document ID: US8541831B2
- Status: Granted
- Kind: B2
- Application number: 12/592,869
- Filed: 2009-12-03
- Published: 2010-06-03
- Granted: 2013-09-24
- Earliest claimed: 2008-12-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Soodoo Chae; Myoungbum Lee; HuiChang Moon; Hansoo Kim; JinGyun Kim; Kihyun Kim; Siyoung Choi; Hoosung Cho
- Inventors: Soodoo Chae; Myoungbum Lee; HuiChang Moon; Hansoo Kim; JinGyun Kim; Kihyun Kim; Siyoung Choi; Hoosung Cho
- Web page: https://patentgrep.com/patent/US8541831B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/10: characterised by the top-view layout
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 64/118: {Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

## Claims

### Claim 1

A nonvolatile memory device comprising:
a semiconductor substrate including a memory cell region and a contact region;
a plurality of active pillars extending in the memory cell region perpendicular to the semiconductor substrate;
a plurality of gate electrodes that intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate; and
a plurality of supporters extending in the contact region perpendicular to the semiconductor substrate to penetrate and support at least one or more of the gate electrodes, wherein at least two of the supporters have a different length from each other in the contact region.

### Claim 2 (depends on 1)

The nonvolatile memory device of claim 1, wherein the supporters are formed of dielectric material or semiconductor material.

### Claim 3 (depends on 1)

The nonvolatile memory device of claim 1, wherein the supporters penetrate all or some of the gate electrodes.

### Claim 4 (depends on 1)

The nonvolatile memory device of claim 1, wherein
the gate electrodes are stacked on the semiconductor substrate, with an interlayer dielectric therebetween; and
the areas of the gate electrodes decrease with an increase in the distance from the semiconductor substrate.

### Claim 5 (depends on 1)

The nonvolatile memory device of claim 1, wherein
the gate electrodes are stacked on the semiconductor substrate, with an interlayer dielectric therebetween;
the upper gate electrode among the gate electrodes exposes an edge portion of the lower gate electrode; and
the supporters are disposed at the exposed edge portion of the lower gate electrode.

### Claim 6 (depends on 1)

The nonvolatile memory device of claim 1, wherein the length of the supporters decreases from the center of the gate electrodes toward the edge.

### Claim 7 (depends on 1)

The nonvolatile memory device of claim 1, wherein the active pillars penetrate the gate electrodes or intersect one sidewall of the gate electrodes.

### Claim 8 (depends on 1)

The nonvolatile memory device of claim 1, wherein the contact region is disposed around the memory cell region.

### Claim 9 (depends on 1)

The nonvolatile memory device of claim 1, wherein the contact region is disposed at both side portions of the memory cell region.

### Claim 10 (depends on 1)

The nonvolatile memory device of claim 1, wherein
the active pillars are arranged two-dimensionally on the semiconductor substrate; and
the gate electrode is connected to at least four or more of the two-dimensionally arranged active pillars or to at least two or more of the one-dimensionally arranged active pillars.