# US 8,541,827 B2 · Semiconductor memory device including multi-layer gate structure

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- Number: US 8,541,827 B2
- Document ID: US8541827B2
- Status: Granted
- Kind: B2
- Application number: 13/653,060
- Filed: 2012-10-16
- Published: 2013-02-14
- Granted: 2013-09-24
- Earliest claimed: 2001-11-16
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Toshitake Yaegashi
- Inventors: Toshitake Yaegashi
- Web page: https://patentgrep.com/patent/US8541827B2

## CPC

- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10B 41/30: characterised by the memory core region
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.

## Claims

### Claim 1

A semiconductor memory device comprising:
(a) a first transistor formed on an upper surface of a substrate;
(b) a first stepped portion disposed adjacent to one side of a gate of the first transistor such that the first stepped portion forms a cavity in the upper surface of said substrate in a first direction;
(c) a first contact plug formed in a region of the first stepped portion, the first contact plug being partially in contact with the first stepped portion; and
(d) an insulating film in a trench in a second direction crossing to the first direction,
wherein an upper surface of the insulating film is higher than the upper surface of said substrate in the cavity.

### Claim 2 (depends on 1)

The device according to claim 1, further comprising a first insulating film formed between the first contact plug and the gate of the first transistor, the first insulating film being partially in contact with the first stepped portion.

### Claim 3 (depends on 2)

The device according to claim 2, further comprising:
a plurality of second transistors formed on an upper surface of a substrate in the first direction, and
second stepped portions disposed between gate electrodes of the plurality of the second transistors.

### Claim 4 (depends on 1)

The device according to claim 1, further comprising a second transistor formed on an upper surface of a substrate adjacent to the first transistor in the first direction,
wherein the upper surface of said substrate in the cavity is lower than that of said substrate between the first transistor and the second transistor.

### Claim 5 (depends on 4)

The device according to claim 4, wherein the first transistor includes a first gate insulating film,
the second transistor includes a second gate insulating film, and
the first and second gate insulating films are the same gate insulating films formed at a same time.

### Claim 6 (depends on 5)

The device according to claim 5, wherein a height of the first stepped portion is larger than a thickness of the second gate insulating film.

### Claim 7 (depends on 4)

The device according to claim 4, wherein two or more of the second transistor are disposed, and the second transistors are connected in series.

### Claim 8 (depends on 1)

The device according to claim 1, wherein the first transistor includes a first gate insulating film, and
a height of the first stepped portion is larger than a thickness of the first gate insulating film.

### Claim 9 (depends on 1)

The device according to claim 1, wherein the first transistor includes a first gate electrode, and
the first stepped portion is positioned outside an edge of the first gate electrode.

### Claim 10 (depends on 1)

The device according to claim 1, wherein the first transistor includes a first gate electrode, and
the first contact plug is formed in a self-aligning manner with respect to the first gate electrode.

### Claim 11 (depends on 1)

The device according to claim 1, further comprising a plurality of second transistors formed on an upper surface of a substrate in the first direction, and
the upper surface of said substrate between the second transistors is higher than the upper surface of said substrate in the cavity.

### Claim 12 (depends on 11)

The device according to claim 11, wherein the upper surface of said substrate between the second transistors is at a same level as an interface between a gate insulating film of the second transistor and the upper surface of the substrate.