# US 8,541,824 B2 · Electronic devices and systems, and methods for making and using the same

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- Number: US 8,541,824 B2
- Document ID: US8541824B2
- Status: Granted
- Kind: B2
- Application number: 13/553,593
- Filed: 2012-07-19
- Published: 2012-11-29
- Granted: 2013-09-24
- Earliest claimed: 2009-09-30
- Assignees: SuVolta, Inc.
- Applicants: Scott E. Thompson; Damodar R. Thummalapally
- Inventors: Scott E. Thompson; Damodar R. Thummalapally
- Web page: https://patentgrep.com/patent/US8541824B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10B 10/00: Static random access memory [SRAM] devices
- H10B 10/12: {comprising a MOSFET load element}
- H10D 30/027: {of lateral single-gate IGFETs}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 30/637: {Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/314: {having vertical doping variations (vertical IGFETs H10D30/63)}
- H10D 62/364: {of IGFETs}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0156: {Manufacturing their doped wells}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/854: {comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention}
- H10D 86/01: Manufacture or treatment
- H10D 89/10: Integrated device layouts
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

## Claims

### Claim 1

A field effect transistor (FET) formed in a doped well, the FET having a source, a drain, and a gate stack having a gate length, the FET comprising:
a screening region positioned above the doped well, the screening region being doped with a first type of dopant to have a dopant concentration between 5×1018 to 1×1020 atoms/cm3, the screening region being electrically coupled to the doped well, the screening region being positioned below the gate to set a depletion depth;
a substantially undoped semiconductive layer formed above the screening region, the substantially undoped semiconductive layer being adjacent to the screening region;
a threshold voltage setting region in the substantially undoped semiconductive layer, the threshold voltage setting region being doped with the first type of dopant, the threshold voltage setting region dopant concentration modifying the threshold voltage of the FET;
wherein the gate stack has a length Lg and is positioned above the doped well to control conduction between a drain and a source, the source and the drain being doped with a second type of dopant;
wherein at least a portion of the substantially undoped semiconductive layer is maintained as a substantially undoped channel region having a first dopant concentration less than 1/10 of the screening region dopant concentration, with the substantially undoped channel region laterally positioned between the source and the drain and vertically positioned between the gate stack and the threshold voltage setting region, and the threshold voltage setting region is vertically positioned between the substantially undoped channel region and the screening region.

### Claim 2 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the substantially undoped semiconductive layer comprises a substantially undoped epitaxial layer.

### Claim 3 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the screening region is positioned at a depth below the gate greater than or equal to Lg/3 to set the depletion depth.

### Claim 4 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the screening region has a dopant concentration between 5×1018 to 5×1019 atoms/cm3.

### Claim 5 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the screening region includes dopants implanted into the doped well and the substantially undoped semiconductive layer comprises a substantially undoped epitaxial layer above the screening region implanted into the doped well.

### Claim 6 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the screening region is substantially coextensive with the substantially undoped channel region.

### Claim 7 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the screening region contacts the source and drain.

### Claim 8 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the threshold voltage setting region has a dopant concentration less than ½ of the screening region dopant concentration.

### Claim 9 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the threshold voltage setting region abuts the screening region.

### Claim 10 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the threshold voltage setting region is substantially coextensive with the substantially undoped channel region.

### Claim 11 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the threshold voltage setting region contacts the source and the drain.

### Claim 12 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the screening region has a thickness greater than 5 nm.

### Claim 13 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the screening region has a thickness greater than 30 nm and less than 80 nm.

### Claim 14 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the threshold voltage setting region having a thickness greater than 5 nm.

### Claim 15 (depends on 1)

The FET formed in a well according to claim 1, wherein the threshold voltage setting region has a thickness greater than 5 nm and less than 30 nm.

### Claim 16 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the screening region includes two or more implanted dopant materials of the first dopant type in the doped well.

### Claim 17 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the substantially undoped channel region has a thickness greater than 5 nm.

### Claim 18 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the substantially undoped channel region has a thickness greater than 5 nm and less than 30 nm.

### Claim 19 (depends on 1)

The FET formed in a dope well according to claim 1, further comprising a first dopant migration resistant layer positioned above the screening region, the first dopant migration resistant layer preventing a dopant migration from the screening region into the threshold voltage setting region.

### Claim 20 (depends on 1)

The FET formed in a dope well according to claim 1, further comprising a second dopant migration resistant layer above the threshold voltage setting region, the second dopant migration resistant layer preventing a dopant migration from the threshold voltage setting region into the substantially undoped channel region.

### Claim 21 (depends on 1)

The FET formed in a dope well according to claim 1, further comprising a third dopant migration resistant layer below the screening region, the third dopant migration resistant layer preventing a dopant migration from the screening region into the doped well.

### Claim 22 (depends on 1)

The FET formed in a dope well according to claim 1, further comprising a deposited gate metal having a work function intermediate between band edge and midgap.

### Claim 23 (depends on 1)

The FET formed in a dope well according to claim 1, further comprising spacers defined around the gate, and wherein the screening region substantially extends between edges of the spacers.

### Claim 24 (depends on 1)

The FET formed in a dope well according to claim 1, further comprising spacers defined around the gate, and wherein the threshold voltage setting region substantially extends between edges of the spacers.

### Claim 25 (depends on 1)

The FET formed in a dope well according to claim 1, further comprising:
a plurality of FETs, each FET having a doped well, a screening region, a threshold voltage setting region, and a substantially undoped channel region;
shallow trench isolation structures positioned to isolate at least some of the plurality of doped wells from each other;
wherein the shallow trench isolation structures are defined to extend completely through the substantially undoped semiconductive layer.

### Claim 26 (depends on 1)

The FET formed in a dope well according to claim 1, wherein the screening region, the threshold voltage setting region, and the substantially undoped channel region are formed by in-situ doping during a single epitaxial layer growth to form the screening region, the threshold voltage setting region, and the substantially undoped channel region.

### Claim 27

A field effect transistor (FET) comprising:
a PMOS screening region electrically coupled to a n-type doped well, the PMOS screening region being positioned under a gate of a PMOS field effect transistor (FET), the PMOS screening region being doped with n-type dopants to have a dopant concentration between 5×1018 to 1×1020 atoms/cm3, the PMOS screening region being positioned below the gate of the PMOS FET to set a depletion depth;
a NMOS screening region electrically coupled to a p-type doped well, the NMOS screening region being positioned under a gate of a NMOS FET, the NMOS screening region being doped with p-type dopants to have a dopant concentration between 5×1018 to 1×1020 atoms/cm3, the NMOS screening region being positioned below the gate of the NMOS FET to set a depletion depth;
a substantially undoped semiconductive layer above the PMOS screening region and the NMOS screening region, the substantially undoped semiconductive layer abutting the PMOS screening region and the NMOS screening region;
a PMOS threshold voltage setting region in the substantially undoped semiconductive layer, the PMOS threshold voltage setting region being doped with n-type dopants, the PMOS threshold voltage setting region dopant concentration modifying a threshold voltage of the PMOS FET;
wherein at least a portion of the undoped semiconductive layer overlying the PMOS threshold voltage setting region is maintained as a substantially undoped PMOS channel region of the PMOS FET, the substantially undoped. PMOS channel region having a dopant concentration less than 1/10 of the PMOS screening region dopant concentration;
a NMOS threshold voltage setting region in the substantially undoped semiconductive layer, the NMOS threshold voltage setting region being doped with p-type dopants, the NMOS threshold voltage setting region dopant concentration modifying a threshold voltage of the NMOS FET;
wherein at least a portion of the undoped semiconductive layer overlying the NMOS threshold voltage setting region is maintained as a substantially undoped NMOS channel region of the NMOS FET, the substantially undoped NMOS channel region having a dopant concentration less than 1/10 of the NMOS screening region dopant concentration;
an isolation region separating the PMOS FET and the NMOS FET formed to pass through the substantially undoped semiconductive layer,
wherein the PMOS threshold voltage setting region is positioned between the substantially undoped PMOS channel region and the PMOS screening region, and the NMOS threshold voltage setting region is positioned between the substantially undoped NMOS channel region and the NMOS screening region.