# US 8,541,823 B2 · Field effect transistor

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- Number: US 8,541,823 B2
- Document ID: US8541823B2
- Status: Granted
- Kind: B2
- Application number: 13/179,635
- Filed: 2011-07-11
- Published: 2011-11-03
- Granted: 2013-09-24
- Earliest claimed: 2005-04-06
- Assignees: International Business Machines Corporation
- Applicants: Toshiharu Furukawa; Mark C. Hakey; Steven J. Holmes; David V. Horak; Charles W. Koburger, III
- Inventors: Toshiharu Furukawa; Mark C. Hakey; Steven J. Holmes; David V. Horak; Charles W. Koburger, III
- Web page: https://patentgrep.com/patent/US8541823B2

## CPC

- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/6715: {characterised by the doping profiles, e.g. having lightly-doped source or drain extensions}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/675: {Gate sidewall spacers}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- Y10S 977/742: Carbon nanotubes, CNTs
- Y10S 977/847: Surface modifications, e.g. functionalization, coating
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.

## Claims

### Claim 1

A transistor, comprising:
a doped well in a substrate, said doped well extending from a top surface of said substrate into said substrate a distance less than the thickness of said substrate;
a gate dielectric layer on a top surface of said doped well region;
a polysilicon gate electrode on a top surface of said gate dielectric layer;
spacers formed on opposite sidewalls of said polysilicon gate electrode;
source/drain extensions formed on opposite sides of said polysilicon gate electrode in said doped well region;
source/drains formed on opposite sides of said polysilicon gate electrode in said doped well region;
buried doped regions formed on opposite sides of said polysilicon gate electrode in said doped well region, said buried doped regions further from said polysilicon gate electrode than said source/drains and said source/drain extensions;
a first doped region in said polysilicon gate electrode, said first doped region extending into said polysilicon gate electrode from a top surface of said polysilicon gate electrode;
a second doped region in said polysilicon gate electrode, said second doped region abutting a bottom surface of said first doped region;
a third doped region in said polysilicon gate electrode, said third doped region between said second doped region and said gate dielectric layer;
a fourth region of said polysilicon gate electrode abutting said second doped region and abutting said third doped region; and
a fifth region of said polysilicon gate electrode abutting third doped region and abutting said gate dielectric layer.

### Claim 2 (depends on 1)

The transistor of claim 1, wherein said polysilicon gate electrode is between about 100 nm and about 150 nm thick measured from said top surface of said polysilicon electrode to said gate dielectric layer and said second doped region is centered between about 30 nm and about 60 nm from said top surface of said polysilicon gate electrode.

### Claim 3 (depends on 1)

The transistor of claim 1, wherein said source/drain extensions, said source/drains, said buried doped regions, said first doped region, said second doped region and said third doped region are all doped the same type and of an opposite type from a doping type of said doped well region.

### Claim 4 (depends on 1)

The transistor of claim 1, wherein said substrate is a bulk silicon substrate or a silicon-on-insulator substrate.

### Claim 5 (depends on 1)

The transistor of claim 1, wherein said source/drains extend from said top surface of said substrate into said doped well further than said source/drain extensions and said buried doped regions extend into said doped well further than said source/drain region.

### Claim 6 (depends on 1)

The transistor of claim 1, wherein source/drain extensions extend under said polysilicon gate electrode and said source/drains and said buried doped regions do not extend under said gate electrode.

### Claim 7 (depends on 1)

The transistor of claim 1, wherein said source/drains, said source/drain extensions, said buried doped regions, said first doped region, said second doped region and said third doped region are all doped the same type and of an opposite type from a doping type of said doped well region and wherein said fourth and fifth regions are undoped.

### Claim 8 (depends on 1)

The transistor of claim 1, further including:
trench isolation formed in said substrate, said source/drain extensions, said source/drains and said buried doped regions abutting said trench isolation.

### Claim 9 (depends on 8)

The transistor of claim 8, wherein said trench isolation extends into said substrate past said doped well.

### Claim 10 (depends on 1)

The transistor of claim 1, wherein said fourth and fifth regions of said polysilicon gate electrode are intrinsic.

### Claim 11 (depends on 1)

The transistor of claim 1, wherein said fourth and fifth doped regions of said polysilicon gate electrode are doped and are not doped greater than about 1E15 atoms/cm3.

### Claim 12 (depends on 1)

The transistor of claim 1, wherein said gate dielectric layer comprises a material selected from the group consisting of a metal silicate, HfSixOy,HfSixOyNz, a metal oxide, Al2O3, HfO2, ZrO2, Ta2O5, BaTiO3, and combinations of layers thereof.

### Claim 13 (depends on 1)

The transistor of claim 1, wherein said source/drain extensions extend under said polysilicon gate electrode and said source/drains do not extend under said gate electrode.

### Claim 14 (depends on 1)

The transistor of claim 1, wherein said top surface of said gate electrode is flat.

### Claim 15 (depends on 1)

The transistor of claim 1, wherein said polysilicon gate electrode has a height of about 100 nm to about 150 nm and a width of about 50 nm to about 500 nm.

### Claim 16 (depends on 1)

The transistor of claim 1, wherein said fourth and fifth regions of said polysilicon gate electrode are doped and are not doped greater than about 1E16 atoms/cm3.

### Claim 17 (depends on 1)

The transistor of claim 1, wherein herein said source/drains, said source/drain extensions, said buried doped regions, said first doped region, said second doped region and said third doped region are all doped with a same dopant selected from the group consisting of arsenic, phosphorous and boron.

### Claim 18 (depends on 8)

The transistor of claim 8, wherein said trench isolation extends into said substrate past said doped well and said doped well abuts a semiconductor region of said substrate.