# US 8,541,822 B2 · Semiconductor device and method for producing the same

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- Number: US 8,541,822 B2
- Document ID: US8541822B2
- Status: Granted
- Kind: B2
- Application number: 12/591,340
- Filed: 2009-11-17
- Published: 2010-05-27
- Granted: 2013-09-24
- Earliest claimed: 2008-11-21
- Assignees: Sharp Kabushiki Kaisha
- Applicants: Masayuki Tajiri
- Inventors: Masayuki Tajiri
- Web page: https://patentgrep.com/patent/US8541822B2

## CPC

- H10P 30/204: {into Group IV semiconductors}
- H10D 30/027: {of lateral single-gate IGFETs}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10P 30/208: {of electrically inactive species}
- H10D 30/0212: {using self-aligned silicidation}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device comprising at least two wiring layers on a substrate or a surface layer of the substrate, wherein a lower wiring layer of the two wiring layers contains silicon, and a silicon carbide layer is placed between the lower wiring layer and an upper wiring layer.

## Claims

### Claim 1

A semiconductor device comprising:
at least two wiring layers on a silicon substrate or a surface layer of the silicon substrate, wherein a lower wiring layer of the two wiring layers contains silicon;
a silicon carbide layer between the lower wiring layer and an upper wiring layer;
a gate electrode located on the silicon substrate via a gate insulating film;
a channel located on a surface layer of the silicon substrate under the gate electrode;
a pair of drift layers having the channel therebetween in a channel-length direction; and
silicon layers located on each of the pair of drift layers and working as a source/drain, wherein
the lower wiring layer is the pair of drift layers and the upper wiring layer is the source/drain.

### Claim 2 (depends on 1)

The semiconductor device as set forth in claim 1, wherein the silicon carbide layer is located on a surface layer of the lower wiring layer, and a peak of a concentration of carbon atoms forming the silicon carbide layer is at a position 5 nm to 50 nm deep from a surface of the lower wiring layer.

### Claim 3 (depends on 2)

The semiconductor device as set forth in claim 2, wherein the silicon carbide layer contains carbon atoms in a peak concentration of 1×1020/cm3 to 1×1022/cm3.

### Claim 4

A method for producing a semiconductor device, the semiconductor device comprising:
a gate electrode located on a silicon substrate via a gate insulating film;
a channel located on a surface layer of the silicon substrate under the gate electrode;
a pair of drift layers having the channel therebetween in a channel-length direction; and
a silicon layer located on each of the pair of drift layers and working as a source/drain, wherein
a lower wiring layer is the pair of drift layers, an upper wiring layer is the source/drain, and the silicon carbide layer is located between the drift layers and the source/drain,
the method comprising the steps of:
forming a silicon carbide layer on the lower wiring layer or a surface layer of the lower wiring layer, the lower wiring layer being composed of silicon and formed on the silicon substrate or a surface layer of the silicon substrate; and
forming the upper wiring layer on the silicon carbide layer;
wherein the lower wiring layer is the pair of drift layers and the upper wiring layer is the source/drain.

### Claim 5 (depends on 4)

The method for producing a semiconductor device as set forth in claim 4, wherein the silicon carbide layer is located on the surface layer of the lower wiring layer and formed by implanting carbon atoms to the lower wiring layer at an acceleration energy of 0.6 keV to 12 keV.

### Claim 6 (depends on 5)

The method for producing a semiconductor device as set forth in claim 5, wherein the silicon carbide layer is formed by implanting carbon atoms in a dose of 3×1015/cm2 to 3×1017/cm2.