# US 8,541,817 B2 · Multilayer barrier III-nitride transistor for high voltage electronics

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- Number: US 8,541,817 B2
- Document ID: US8541817B2
- Status: Granted
- Kind: B2
- Application number: 12/941,332
- Filed: 2010-11-08
- Published: 2011-05-12
- Granted: 2013-09-24
- Earliest claimed: 2009-11-06
- Assignees: Nitek, Inc.
- Applicants: Qhalid Fareed; Vinod Adivarahan; Asif Khan
- Inventors: Qhalid Fareed; Vinod Adivarahan; Asif Khan
- Web page: https://patentgrep.com/patent/US8541817B2

## CPC

- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 62/852: being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An improved high breakdown voltage semiconductor device and method for manufacturing is provided. The device has a substrate and a AlaGa1-aN layer on the substrate wherein 0.1≦a≦1.00. A GaN layer is on the AlaGa1-aN layer. An In1-bGabN/GaN channel layer is on the GaN layer wherein 0.1≦b≦1.00. A AlcIndGa1-c-dN spacer layer is on the In1-bGabN/GaN layer wherein 0.1≦c≦1.00 and 0.0≦d≦0.99. A AleIn1-eN nested superlattice barrier layer is on the AlcIndGa1-c-dN spacer layer wherein 0.10≦e≦0.99. A AlfIngGa1-f-gN leakage suppression layer is on the AleIn1-eN barrier layer wherein 0.1≦f≦0.99 and 0.1≦g≦0.99 wherein the leakage suppression layer decreases leakage current and increases breakdown voltage during high voltage operation. A superstructure, preferably with metallic electrodes, is on the AlfIngGa1-f-gN leakage suppression layer.

## Claims

### Claim 1

A high breakdown voltage semiconductor device comprising:
a substrate;
a AlaGa1-aN layer on said substrate wherein 0.1≦a≦1.00;
a GaN layer on said AlaGa1-aN layer;
a In1-bGabN/GaN channel layer on said GaN layer wherein 0.1≦b≦1.00;
an AlcIndGa1-c-dN spacer layer on said In1-bGabN/GaN layer wherein 0.1≦c≦1.00 and 0.0≦d≦0.99;
a AleIn1-eN nested superlattice barrier layer on said AlcIndGa1-c-dN spacer layer wherein 0.10≦e≦0.99;
a AlfIngGa1-f-gN leakage suppression layer over on said AleIn1-eN barrier layer wherein 0.1≦f≦0.99 and 0.1≦g≦0.99 wherein said leakage suppression layer decreases leakage current and increases breakdown voltage during high voltage operation; and
a superstructure on said AlfIngGa1-f-gN leakage suppression layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1 wherein said superstructure comprises a source electrode, a drain electrode and a gate electrode.

### Claim 3 (depends on 2)

The semiconductor device of claim 2 wherein said superstructure further comprises a functional layer.

### Claim 4 (depends on 3)

The semiconductor of claim 3 further comprising at least one of a source electrode, a gate electrode or a drain electrode on said functional layer.

### Claim 5 (depends on 3)

The semiconductor device of claim 3 further comprising a field plate formed on at least one of said source, drain and gate electrode.

### Claim 6 (depends on 3)

The semiconductor device of claim 3 wherein said functional layer comprises at least one material selected from the group consisting of silicon dioxide, silicon nitride, benzocyclobutene, aluminium nitride, aluminum galium nitride, galium nitride, boron nitride, silicon carbide, diamond, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, scandium oxide, polytetrafluoroethylene, perfluoroalkoxy, fluorinated ethylene propylene, polystyrene, polyoxybenzylmethylenglycolanhydride, or combinations thereof.

### Claim 7 (depends on 6)

The semiconductor device of claim 6 wherein said functional layer is a high dielectric insulator.

### Claim 8 (depends on 7)

The semiconductor device as in claim 7 wherein said functional layer has a dielectric strength of at least 1 MV/m but no more than 100 MV/m.

### Claim 9 (depends on 1)

The semiconductor device of claim 1 wherein said substrate is selected from the group consisting of sapphire, the substrate may be made of silicon carbide, GaN, AlN, AlGaN, InN, InGaN, AlInGaN, Silicon, GaAs, LiAlO3, LiGaO3, ZnO, and a metal.

### Claim 10 (depends on 9)

The semiconductor device of claim 9 wherein said substrate is semi-insulating SiC.

### Claim 11 (depends on 1)

The semiconductor device of claim 1 wherein 0.90≦a≦1.00.

### Claim 12 (depends on 1)

The semiconductor device of claim 1 wherein said a AlaGa1-aN layer has a thickness of 10 Å-10 μm.

### Claim 13 (depends on 1)

The semiconductor device of claim 1 wherein said GaN layer has a thickness of 10 Å-10 μm.

### Claim 14 (depends on 1)

The semiconductor device of claim 1 wherein said In1-bGabN/GaN channel layer has a thickness of 10 Å-1000 Å.

### Claim 15 (depends on 1)

The semiconductor device of claim 1 wherein 0.90≦c≦1.00 and 0≦d≦0.10.

### Claim 16 (depends on 1)

The semiconductor device of claim 1 wherein said AlcIndGa1-c-dN spacer has a thickness of at least 5 Å to no more than 100 Å.

### Claim 17 (depends on 16)

The semiconductor device of claim 16 wherein said AlcIndGa1-c-dN spacer has a thickness of at least 10 Å to no more than 20 Å.

### Claim 18 (depends on 1)

The semiconductor device of claim 1 wherein said AleIn1-eN nested superlattice barrier layer has a thickness of at least 1 Å to no more than 1000 Å.

### Claim 19 (depends on 1)

The semiconductor device of claim 1 wherein said AleIn1-eN nested superlattice barrier layer has a thickness of at least 30 Å to no more than 300 Å.

### Claim 20 (depends on 1)

The semiconductor device of claim 1 wherein said nested superlattice barrier layer comprises sublayers.

### Claim 21 (depends on 20)

The semiconductor device of claim 20 wherein said sublayers comprise alternating AlN/InN layers.

### Claim 22 (depends on 21)

The semiconductor device of claim 21 wherein each AlN layer has a thickness of at least 1 Å to no more than 500 Å.

### Claim 23 (depends on 22)

The semiconductor device of claim 22 wherein each AlN layer has a thickness of 1 Å to 100 Å.

### Claim 24 (depends on 23)

The semiconductor device of claim 23 wherein each AlN layer has a thickness of 1 Å to 20 Å.

### Claim 25 (depends on 21)

The semiconductor device of claim 21 wherein each InN layer has a thickness of 1 Å to 500 Å.

### Claim 26 (depends on 25)

The semiconductor device of claim 25 wherein each InN layer has a thickness of 1 Å to 100 Å.

### Claim 27 (depends on 26)

The semiconductor device of claim 26 wherein each InN layer has a thickness of 1 Å to 20 Å.

### Claim 28 (depends on 20)

The semiconductor device of claim 20 wherein adjacent AlN layers have different compositions.

### Claim 29 (depends on 18)

The semiconductor device of claim 18 wherein said AleIn1-eN nested superlattice barrier layer comprises individual or multi-stacks of Al/N/In/N atomic layers.

### Claim 30 (depends on 29)

The semiconductor device of claim 29 wherein said individual or multi-stacks of Al/N/In/N atomic layers each have a thickness of 1 Å-20 Å.

### Claim 31 (depends on 1)

The semiconductor device of claim 1 wherein 0.6≦e≦0.99.

### Claim 32 (depends on 1)

The semiconductor device of claim 1 wherein said AlfIngGa1-f-gN leakage suppression layer has a thickness of at least 1 Å to no more than 200 Å.

### Claim 33 (depends on 1)

The semiconductor device of claim 1 wherein said nested superlattice barrier layer is an AlInN nested superlattice barrier layer and said leakage suppression layer is selected from a single layer and multistack layers with each multistack layer of said multistack layers selected from AlN, GaN, AlGaN, InGaN, AlInGaN and AlGaN layer.

### Claim 34 (depends on 33)

The semiconductor device of claim 33 wherein leakage suppression layer is selected from undoped and doped with silicon.

### Claim 35 (depends on 1)

The semiconductor device of claim 1 where the electron mobility is at least 300 cm2/vs to 3000 cm2/vs and the sheet carrier density of 0.1-4.0×1013 cm−2.

### Claim 36 (depends on 1)

The semiconductor device of claim 1 with a sheet resistance of ranging between 10-1000 ohm/sq.

### Claim 37 (depends on 1)

The semiconductor device of claim 1 wherein the breakdown voltage is between 300V to 100 KV.

### Claim 38

A method for forming a semiconductor device comprising the steps of:
providing a substrate;
depositing a AlaGa1-aN layer on said substrate wherein 0.1≦a≦1.00;
depositing a GaN layer on said AlaGa1-aN layer;
depositing a In1-bGabN/GaN channel layer on said GaN layer wherein 0.1≦b≦1.00;
depositing a AlcIndGa1-c-dN spacer layer on said In1-bGabN/GaN layer wherein 0.1≦c≦1.00 and 0≦d≦0.99;
depositing a AleIn1-eN nested superlattice barrier layer on said AlcIndGa1-c-dN spacer layer wherein 0.10≦e≦0.99;
depositing a AlfIngGa1-f-gN leakage suppression layer on said AleIn1-eN barrier layer wherein 0.1≦f≦0.99 and 0.1≦g≦0.99;
depositing at least one layer selected from said AlaGa1-aN layer; said GaN layer, said In1-bGabN/GaN channel layer; said AleIn1-eN nested superlattice barrier layer and said AlfIngGa1-f-gN leakage suppression layer by a pulsed metalorganic chemical vapor deposition technique; and a superstructure on said AlfIngGa1-f-gN leakage suppression layer.

### Claim 39 (depends on 38)

The method for forming a semiconductor device of claim 38 wherein said superstructure comprises a source, a drain and a gate.

### Claim 40 (depends on 39)

The method for forming a semiconductor device of claim 39 further comprising a field electrode on at least one of said source, said drain or said gate.

### Claim 41 (depends on 39)

The method for forming a semiconductor device of claim 39 wherein said functional layer is a dielectric.

### Claim 42 (depends on 39)

The method for forming a semiconductor device of claim 39 wherein said superstructure further comprises a functional layer.

### Claim 43 (depends on 42)

The method for forming a semiconductor device of claim 42 wherein said functional layer is an insulator.

### Claim 44 (depends on 42)

The method for forming a semiconductor device of claim 42 wherein at least one of said source said drain or said gate is on said functional layer.

### Claim 45 (depends on 42)

The method for forming a semiconductor device of claim 42 wherein said functional layer comprises at least one material selected from the group consisting of silicon dioxide, silicon nitride, benzocyclobutene, aluminium nitride, aluminum galium nitride, galium nitride, boron nitride, silicon carbide, diamond, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, scandium oxide, polytetrafluoroethylene, perfluoroalkoxy, fluorinated ethylene propylene, polystyrene, polyoxybenzylmethylenglycolanhydride, or combinations thereof.

### Claim 46 (depends on 5)

The method for forming a semiconductor device of claim 5 wherein said functional layer is a high dielectric insulator.

### Claim 47 (depends on 38)

The method for forming a semiconductor device of claim 38 wherein 0.90≦a≦1.00.

### Claim 48 (depends on 46)

The method for forming a semiconductor device of claim 46 wherein said functional layer has a dielectric strength of at least 1 MV/m but no more than 100 MV/m.

### Claim 49 (depends on 38)

The method for forming a semiconductor device of claim 38 wherein said substrate is selected from the group consisting of sapphire, the substrate may be made of silicon carbide, GaN, AlN, AlGaN, InN, InGaN, AlInGaN, Silicon, GaAs, LiAlO3, LiGaO3, ZnO, and a metal.

### Claim 50 (depends on 49)

The method for forming a semiconductor device of claim 49 wherein said substrate is silicon carbide substrate.

### Claim 51 (depends on 38)

The method for forming a semiconductor device of claim 38 wherein 0.90≦c≦1.00 and 0.0≦d≦1.00.

### Claim 52 (depends on 38)

The method for forming a semiconductor device of claim 38 wherein said a AlaGa1-aN layer has a thickness of at least 10 Å to no more than 1.0 μm.

### Claim 53 (depends on 38)

The method for forming a semiconductor device of claim 38 wherein said GaN layer has a thickness of at least 10 Å to no more than 10 μm.

### Claim 54 (depends on 38)

The method for forming a semiconductor device of claim 38 wherein said In1-bGabN/GaN channel layer has a thickness of at least 10 Å to no more than 1000 Å.

### Claim 55 (depends on 38)

The method for forming a semiconductor device of claim 38 wherein said AlcIndGa1-c-dN spacer has a thickness of at least 5 Å to no more than 100 Å.

### Claim 56 (depends on 55)

The method for forming a semiconductor device of claim 55 wherein said AlcIndGa1-c-dN spacer has a thickness of at least 10 Å to no more than 20 Å.

### Claim 57 (depends on 38)

The method for forming a semiconductor device of claim 38 wherein said AleIn1-eN nested superlattice barrier layer has a thickness of at least 1 Å to no more than 1000 Å.

### Claim 58 (depends on 57)

The method for forming a semiconductor device of claim 57 wherein said AleIn1-eN nested superlattice barrier layer has a thickness of at least 30 Å to no more than 300 Å.

### Claim 59 (depends on 38)

The method for forming a semiconductor device of claim 38 wherein said AleIn1-eN nested superlattice barrier layer comprising alternating AlN/InN layers.

### Claim 60 (depends on 59)

The method for forming a semiconductor device of claim 59 wherein each AlN layer has a thickness of 1 Å to 500 Å.

### Claim 61 (depends on 60)

The method for forming a semiconductor device of claim 60 wherein each AlN layer has a thickness of 1 Å to 100 Å.

### Claim 62 (depends on 61)

The method for forming a semiconductor device of claim 61 wherein each AlN layer has a thickness of 1 Å to 20 Å.

### Claim 63 (depends on 59)

The method for forming a semiconductor device of claim 59 wherein each InN layer has a thickness of 1 Å to 500 Å.

### Claim 64 (depends on 63)

The method for forming a semiconductor device of claim 63 wherein each InN layer has a thickness of 1 Å to 100 Å.

### Claim 65 (depends on 64)

The method for forming a semiconductor device of claim 64 wherein each InN layer has a thickness of 1 Å to 20 Å.

### Claim 66 (depends on 38)

The method for forming a semiconductor device of claim 38 wherein said AleIn1-eN nested superlattice barrier layer comprises individual or multi-stacks of Al/N/In/N atomic layers.

### Claim 67 (depends on 66)

The method for forming a semiconductor device of claim 66 wherein said individual or multi-stacks of Al/N/In/N atomic layers each have a thickness of 1 Å-20 Å.

### Claim 68 (depends on 38)

The method for forming a semiconductor device of claim 38 wherein 0.65≦e≦0.99.

### Claim 69 (depends on 38)

The method for forming a semiconductor device of claim 38 wherein said AlfIngGa1-f-gN leakage suppression layer has a thickness of at least 1 Å to no more than 200 Å.

### Claim 70 (depends on 38)

The method of forming a semiconductor device of claim 38 wherein at least one layer is formed by a technique selected from metalorganic chemical vapor deposition, hydride vapor phase epitaxy, pulsed atomic layer epitaxy, rapid pulsed lateral overgrowth epitaxy, molecular beam epitaxy, metalorganic hydride vapor phase epitaxy and flow modulation technique.

### Claim 71 (depends on 38)

The method for forming a semiconductor device of claim 38 where the electron mobility is at least 300 cm2/vs to 3000 cm2/vs and the sheet carrier density of 0.1-4.0×1013 cm−2.

### Claim 72 (depends on 38)

The method for forming a semiconductor device of claim 38 with a sheet resistance of ranging between 10-1000 ohm/sq.

### Claim 73 (depends on 38)

The method for forming a semiconductor device of claim 38 wherein the breakdown voltage is between 300V to 100 KV.