# US 8,541,814 B2 · Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers

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- Number: US 8,541,814 B2
- Document ID: US8541814B2
- Status: Granted
- Kind: B2
- Application number: 13/084,594
- Filed: 2011-04-12
- Published: 2012-10-18
- Granted: 2013-09-24
- Earliest claimed: 2011-04-12
- Assignees: International Business Machines Corporation
- Applicants: Dureseti Chidambarrao; Ramachandran Muralidhar; Philip J Oldiges; Viorel Ontalus
- Inventors: Dureseti Chidambarrao; Ramachandran Muralidhar; Philip J Oldiges; Viorel Ontalus
- Web page: https://patentgrep.com/patent/US8541814B2

## CPC

- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/01: Manufacture or treatment
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor. Accordingly, the application of dielectric spacers and epitaxial layers to minimize leakage current and transistor junction capacitance in CMOS transistors can enhance the utility and performance of the CMOS transistors in low power applications.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
gates disposed on the substrate and spaced at a distance from each other, wherein a first dielectric spacer is disposed on and adjacent to the gate;
one or more trenches in the substrate between each of the gates;
a second dielectric spacer disposed on and adjacent to the first dielectric spacer and the substrate between the gates, wherein a portion of the second dielectric spacer is removed; and
one or more epitaxial layers disposed on and adjacent to the second dielectric spacer and a portion of the substrate between the gates, wherein a selective portion of the substrate that is below all the one or more epitaxial layers further comprises a junction-butting implant layer that is doped with an opposite doping type than the substrate doping type.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device further comprises a complementary metal-oxide-semiconductor (CMOS) field effect transistor.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the substrate comprises bulk silicon or silicon-on-insulator, and wherein the portion of the substrate is doped with p-type or n-type dopants.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein extensions are formed in a portion of the substrate, below a portion of the gates, and between the gates.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the one or more trenches are formed utilizing reactive ion etching (RIE), anisotropic RIE, isotropic RIE, wet etching, plasma etching, or ion milling.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the first dielectric spacer and the second dielectric spacer includes nitride, oxide, or any other dielectric material.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein:
the portion of the second dielectric spacer that is removed provides a gap region for current to flow;
the second dielectric spacer minimizes the size of the interface between the one or more epitaxial layers and the substrate, which also minimizes transistor junction capacitance and minimizes leakage current during periods of time when the complementary metal-oxide-semiconductor (CMOS) field effect transistor is off; and
the second dielectric spacer minimizes lateral straggle of ions during ion implantation or other conventional doping techniques.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein:
the one or more epitaxial layers comprise silicon-germanium,
silicon-germanium doped with p-type dopants, silicon-carbide, or silicon-carbide doped with n-type dopants; and
the one or more epitaxial layers are doped utilizing techniques that include ion implantation and anneal, and rapid thermal processing to form extensions, source regions, and drain regions.