# US 8,541,812 B2 · Semiconductor device and method of manufacture thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,541,812 B2 - Document ID: US8541812B2 - Status: Granted - Kind: B2 - Application number: 12/918,542 - Filed: 2009-02-26 - Published: 2011-09-08 - Granted: 2013-09-24 - Earliest claimed: 2008-02-28 - Assignees: NXP B.V. - Applicants: Philippe Meunier-Beillard; Mark C. J. C. M. Kramer; Johannes J. T. M. Donkers; Guillaume Boccardi - Inventors: Philippe Meunier-Beillard; Mark C. J. C. M. Kramer; Johannes J. T. M. Donkers; Guillaume Boccardi - Web page: https://patentgrep.com/patent/US8541812B2 ## CPC - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 10/021: {of heterojunction BJTs [HBT]} - H10D 10/891: {comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 62/137: {Collector regions of BJTs} - H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe - H10D 64/281: {Base electrodes for bipolar transistors} - H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device} - H10D 84/401: {Combinations of FETs or IGBTs with BJTs} - H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge - H10D 64/62: Electrodes ohmically coupled to a semiconductor - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device (10) comprising a bipolar transistor and a field effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22d and 22e) and a base region (33d) of the bipolar transistor. The bipolar transistor is provided with a first insulating cavity (92) provided in the collector region (22d and 22e). The base region (33d) is narrower in the plane of the substrate than the collector region (22d and 22e) due to a second insulating cavity (94) provided around the base region (33d) and between the collector region (22d and 22e) and the emitter region (4). By blocking diffusion from the base region the first insulating cavity (92) provides a reduction in the base collector capacitance and can be described as defining the base contact. ## Claims ### Claim 1 A semiconductor device with a substrate and a semiconductor body comprising a bipolar transistor with, in the following order, a collector region, a base region, and an emitter region, wherein the semiconductor body comprises a projecting mesa within which at least a portion of the collector region and the base region are present and which is surrounded by an isolation region; characterised in that: the semiconductor device further comprises a field effect transistor; the bipolar transistor is provided with a first insulating cavity provided in the collector region; and the base region is narrower in the plane of the substrate than the collector region due to a second insulating cavity provided around the base region and between the collector region and the emitter region. ### Claim 2 (depends on 1) A semiconductor device according to claim 1, comprising a remaining portion of a layer defining the first insulating cavity in the collector region, wherein the remaining portion of said layer is surrounded by the first insulating cavity blocks diffusion from the collector region. ### Claim 3 (depends on 2) A semiconductor device according to claim 2, wherein the remaining portion of the layer defining the first insulating cavity and surrounded by the first insulating cavity is SiGe:C. ### Claim 4 (depends on 1) A semiconductor device according to claim 1, further comprising a dummy emitter. ### Claim 5 (depends on 1) A semiconductor device according to claim 1, wherein the first insulating cavity is filled with a gas. ### Claim 6 (depends on 5) A semiconductor device according to claim 5 wherein the gas is air. ### Claim 7 (depends on 1) A semiconductor device according to claim 1, wherein the first insulating cavity is filled with silicon dioxide. ### Claim 8 A method of manufacturing a semiconductor device with a substrate and a semiconductor body comprising a bipolar transistor with, in the following order, a collector region, a base region, and an emitter region, wherein the semiconductor body comprises a projecting mesa within which at least a portion of the collector region and the base region are present and which is surrounded by an isolation region; characterised by: further providing the semiconductor device with a field effect transistor; providing the bipolar transistor with a first insulating cavity in the collector region; and providing the bipolar transistor with a second insulating cavity, the second insulating cavity being provided around the base region and between the collector region and the emitter region such that the base region is narrower in the plane of the substrate than the collector region. ### Claim 9 (depends on 8) A method according to claim 8, comprising providing a remaining portion of a layer defining the first insulating cavity in the collector region, wherein the remaining portion of said layer is surrounded by the first insulating cavity, for blocking diffusion from the collector region. ### Claim 10 (depends on 9) A method according to claim 9, wherein the remaining portion of the layer defining the first insulating cavity and surrounded by the first insulating cavity is SiGe:C. ### Claim 11 (depends on 8) A method according to claim 8, wherein a dummy emitter is provided. ### Claim 12 (depends on 8) A method according to claim 8, wherein the first insulating cavity is filled with a gas. ### Claim 13 (depends on 12) A method according to claim 12 wherein the gas is air. ### Claim 14 (depends on 8) A method according to claim 8, wherein the first insulating cavity is filled with silicon dioxide. ### Claim 15 (depends on 1) A semiconductor device according to claim 1, further comprising at least one spacer provided adjacent to a portion of the projecting mesa so as to reduce base-collector capacitance. ### Claim 16 (depends on 15) A semiconductor device according to claim 15, wherein the isolating region is lower than the base region. ### Claim 17 (depends on 8) A method according to claim 8, further comprising providing at least one spacer adjacent to a portion of the projecting mesa for reducing base-collector capacitance. ### Claim 18 (depends on 17) A method according to claim 17, wherein the isolating region is etched back lower than the base region.