# US 8,541,782 B2 · Method for evaluating oxide semiconductor and method for manufacturing semiconductor device

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- Number: US 8,541,782 B2
- Document ID: US8541782B2
- Status: Granted
- Kind: B2
- Application number: 12/940,724
- Filed: 2010-11-05
- Published: 2011-05-12
- Granted: 2013-09-24
- Earliest claimed: 2009-11-06
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Shunpei Yamazaki; Akiharu Miyanaga; Tatsuya Honda
- Inventors: Shunpei Yamazaki; Akiharu Miyanaga; Tatsuya Honda
- Web page: https://patentgrep.com/patent/US8541782B2

## CPC

- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Many of the principles of an oxide semiconductor are still unclear and therefore there is no established method for evaluating an oxide semiconductor. Thus, an object is to provide a novel method for evaluating an oxide semiconductor. Carrier density is evaluated, and hydrogen concentration is also evaluated. Specifically, a MOS capacitor (a diode or a triode) is manufactured, and the C-V characteristics of the MOS capacitor are obtained. Then, the carrier density is estimated from the C-V characteristics obtained.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising steps of:
forming a MOS capacitor having a transistor including an oxide semiconductor layer over a substrate;
obtaining a C-V characteristic by plotting a relationship between a gate voltage Vg and a capacitance C of the MOS capacitor;
obtaining a graph by plotting a relationship between the gate voltage Vg and (1/C)2 with the use of the C-V characteristic;
calculating a carrier density Nd by obtaining a differential value of (1/C)2 in a weak inversion region in the graph and substituting the differential value into a mathematical formula:
N
d
=
-
(
2
e
⁢
⁢
ɛ
0
⁢
ɛ
)
/
ⅆ
(
1
/
C
)
2
ⅆ
V
where e is an electron charge ε0 is a vacuum permittivity, and ε is a relative permittivity of the oxide semiconductor layer; and
performing heat treatment of the transistor when the carrier density is determined to be 1×1018 cm−3 or more.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the MOS capacitor is formed by the steps of:
forming a gate insulating layer over a gate electrode;
forming the oxide semiconductor layer over the gate insulating layer; and
forming a source electrode and a drain electrode over the oxide semiconductor layer, wherein the source electrode is electrically connected to the drain electrode.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the heat treatment is performed at a temperature higher than or equal to 150° C.

### Claim 4

A method for manufacturing a semiconductor device, comprising steps of:
forming a MOS capacitor having a transistor including an oxide semiconductor layer over a substrate;
obtaining a C-V characteristic by plotting a relationship between a gate voltage Vg and a capacitance C of the MOS capacitor;
obtaining a graph by plotting a relationship between the gate voltage Vg and (1/C)2 with the use of the C-V characteristic;
calculating a carrier density Nd by obtaining a differential value of (1/C)2 in a weak inversion region in the graph and substituting the differential value into a mathematical formula:
N
d
=
-
(
2
e
⁢
⁢
ɛ
0
⁢
ɛ
)
/
ⅆ
(
1
/
C
)
2
ⅆ
V
where e is an electron charge, ε0 is a vacuum permittivity, and ε is a relative permittivity of the oxide semiconductor layer; and
performing heat treatment of the transistor when the carrier density is determined to be 1×1016 cm−3 or more.

### Claim 5 (depends on 4)

The method according to claim 4, wherein the MOS capacitor is formed by the steps of:
forming a gate insulating layer over a gate electrode;
forming the oxide semiconductor layer over the gate insulating layer; and
forming a source electrode and a drain electrode over the oxide semiconductor layer, wherein the source electrode is electrically connected to the drain electrode.

### Claim 6 (depends on 4)

The method according to claim 4, wherein the heat treatment is performed at a temperature higher than or equal to 150° C.

### Claim 7

A method for manufacturing a semiconductor device, comprising steps of:
forming a MOS capacitor having a transistor including an oxide semiconductor layer over a substrate;
obtaining a C-V characteristic by plotting a relationship between a gate voltage Vg and a capacitance C of the MOS capacitor;
obtaining a graph by plotting a relationship between the gate voltage Vg and (1/C)2 with the use of the C-V characteristic;
calculating a carrier density Nd by obtaining a differential value of (1/C)2 in a weak inversion region in the graph and substituting the differential value into a mathematical formula:
N
d
=
-
(
2
e
⁢
⁢
ɛ
0
⁢
ɛ
)
/
ⅆ
(
1
/
C
)
2
ⅆ
V
where e is an electron charge, ε0 is a vacuum permittivity, and ε is a relative permittivity of the oxide semiconductor layer; and
performing heat treatment of the transistor when the carrier density is determined to be 1×1014 cm−3 or more.

### Claim 8 (depends on 7)

The method according to claim 7, wherein the MOS capacitor is formed by the steps of:
forming a gate insulating layer over a gate electrode;
forming the oxide semiconductor layer over the gate insulating layer; and
forming a source electrode and a drain electrode over the oxide semiconductor layer, wherein the source electrode is electrically connected to the drain electrode.

### Claim 9 (depends on 7)

The method according to claim 7, wherein the heat treatment is performed at a temperature higher than or equal to 150° C.