# US 8,541,776 B2 · Nanostructure-based memory

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- Number: US 8,541,776 B2
- Document ID: US8541776B2
- Status: Granted
- Kind: B2
- Application number: 12/094,850
- Filed: 2006-12-01
- Published: 2009-07-09
- Granted: 2013-09-24
- Earliest claimed: 2005-12-02
- Assignees: The Regents of the University of California
- Applicants: Prabhakar R. Bandaru; Joel Hollingsworth
- Inventors: Prabhakar R. Bandaru; Joel Hollingsworth
- Web page: https://patentgrep.com/patent/US8541776B2

## CPC

- G11C 13/025: {using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C: STATIC STORES (semiconductor memory devices H10B)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Improved memory devices that include one or more nanostructures such as carbon nanotubes or other nanostructures, as well as systems and devices incorporating such improved memory devices, are disclosed. In at least some embodiments, the improved memory device is of a nonvolatile type such as a flash memory device, and employs a pair of triodes that form a memory cell, where each triode employs at least one carbon nanotube. Also disclosed are methods of operating and fabricating such improved memory devices.

## Claims

### Claim 1

A memory device comprising:
a memory cell that includes:
a first triode that includes a first nanostructure;
a second triode that includes a second nanostructure; and
a layer of metal that forms both an anode of the first triode and a cathode of the second triode;
wherein the first nanostructure and the second nanostructure are positioned within a vacuum-sealed region.

### Claim 2 (depends on 1)

The memory device of claim 1 , wherein the first nanostructure is a carbon nanostructure.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the carbon nanostructure is a carbon nanotube (CNT).

### Claim 4 (depends on 1)

The memory device of claim 1 , wherein the memory device is a non-volatile memory device.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the memory device is a flash memory device.

### Claim 6 (depends on 1)

The memory device of claim 1 , wherein the memory device is a random access memory (RAM) device.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the memory device is a read only memory (ROM) device.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the memory device is an alternating current (AC) type device.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the memory cell includes first and second portions having first and second substrates, respectively, wherein the first and second nanostructures are fabricated on the first and second substrates, respectively, and wherein the first and second portions of the memory cell are arranged in relation to one another by way of a flip-chip operation.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein the first nanostructure serves as an erase tip.

### Claim 11 (depends on 1)

A logic device comprising the memory device of claim 1.

### Claim 12 (depends on 11)

A computer employing the logic device of claim 11, wherein the logic device is a NAND gate that can be used to form at least part of a further gate selected from the group consisting of an AND gate, a NOR gate, an OR gate, an XOR gate, or another type of logic gate.

### Claim 13 (depends on 1)

The device of claim 1, wherein the first nanostructure comprises a nanotube, a nanowire, a nanocone, or a nanofiber and the second nanostructure comprises another nanotube, another nanowire, another nanocone, or another nanofiber.

### Claim 14 (depends on 1)

The device of claim 1, wherein the layer of metal forms a plate of a storage capacitor.