# US 8,541,774 B2 · Hybrid CMOS technology with nanowire devices and double gated planar devices

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- Number: US 8,541,774 B2
- Document ID: US8541774B2
- Status: Granted
- Kind: B2
- Application number: 13/605,076
- Filed: 2012-09-06
- Published: 2013-01-31
- Granted: 2013-09-24
- Earliest claimed: 2011-07-25
- Assignees: International Business Machines Corporation
- Applicants: Sarunya Bangsaruntip; Josephine B. Chang; Leland Chang; Jeffrey W. Sleight
- Inventors: Sarunya Bangsaruntip; Josephine B. Chang; Leland Chang; Jeffrey W. Sleight
- Web page: https://patentgrep.com/patent/US8541774B2

## CPC

- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/435: {having multiple laterally adjacent 1D material channels}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 86/01: Manufacture or treatment
- H10D 86/011: {comprising FinFETs}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 86/215: {comprising FinFETs}
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D 64/685: {being perpendicular to the channel plane}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.

## Claims

### Claim 1

A substrate, comprising:
a first source region comprising a first semiconductor layer disposed on a second semiconductor layer, the first source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
a first drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the first drain region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
a plurality of nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members are formed from the first semiconductor layer, and have opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes;
a second source region comprising the first semiconductor layer disposed on the second semiconductor layer, the second source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
a second drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the second drain region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; and
a single channel member suspended by the second source region and the second drain region, where the single channel member is formed from the first semiconductor layer, and has opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes, where a width of the single channel member is at least several times a width of a single nanowire member.

### Claim 2 (depends on 1)

The substrate of claim 1, further comprising a first gate formed around a portion of the nanowire channel members and a second gate formed around a portion of the single channel member.

### Claim 3 (depends on 1)

The substrate of claim 1, further comprising an omega-gate nanowire FET.

### Claim 4 (depends on 3)

The substrate of claim 3, where the omega-gate nanowire FET is formed on a thinned portion of the first semiconductor layer.

### Claim 5 (depends on 1)

The substrate of claim 1, where the first semiconductor layer includes silicon and where the second semiconductor material includes SiGe.

### Claim 6

An integrated circuit comprising a plurality of field effect transistor (FET) devices disposed over a common substrate, said plurality of FET devices comprising:
a first source region comprising a first semiconductor layer disposed on a second semiconductor layer, the first source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
a first drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the first drain region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
a plurality of nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members are formed from the first semiconductor layer, and have opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes;
a second source region comprising the first semiconductor layer disposed on the second semiconductor layer, the second source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
a second drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the second drain region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
a single channel member suspended by the second source region and the second drain region, where the single channel member is formed from the first semiconductor layer, and has opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes; and
a first gate formed around at least a portion of the nanowire channel members and a second gate formed around at least a portion of the single channel member.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, further comprising an omega-gate nanowire FET device.

### Claim 8 (depends on 7)

The integrated circuit of claim 7, where the omega-gate nanowire FET device is formed on a thinned portion of the first semiconductor layer.

### Claim 9 (depends on 6)

The integrated circuit of claim 6, where the first semiconductor layer includes silicon and where the second semiconductor material includes SiGe.

### Claim 10 (depends on 6)

The integrated circuit of claim 6, where a width of the single channel member is at least several times a width of a single nanowire member.

### Claim 11

An integrated circuit comprising:
a plurality of field effect transistor (FET) devices disposed over a common silicon on insulator (SOI) substrate comprising a layer of buried oxide (BOX) having an overlying layer of silicon, said plurality of FET devices comprising:
a first source region comprising a first semiconductor layer disposed on top of a second semiconductor layer that is disposed on top of the layer of silicon, the first source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
a first drain region comprising the first semiconductor layer disposed on top of the second semiconductor layer that is disposed on top of the layer of silicon, the first drain region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
a plurality of nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members are formed from the first semiconductor layer and have opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes;
a second source region comprising the first semiconductor layer disposed on top of the second semiconductor layer that is disposed on top of the layer of silicon, the second source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
a second drain region comprising the first semiconductor layer disposed on top of the second semiconductor layer that is disposed on top of the layer of silicon, the second drain region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
a single channel member suspended by the second source region and the second drain region, where the single channel member is formed from the first semiconductor layer and has opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes, where a width of the single channel member is at least several times a width of a single nanowire member; and
a first gate formed around at least a portion of the nanowire channel members and a second gate formed around at least a portion of the single channel member.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, where the first semiconductor layer includes silicon and where the second semiconductor material includes SiGe.