# US 8,541,765 B2 · Resistance variable memory cell structures and methods > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,541,765 B2 - Document ID: US8541765B2 - Status: Granted - Kind: B2 - Application number: 12/787,018 - Filed: 2010-05-25 - Published: 2011-12-01 - Granted: 2013-09-24 - Earliest claimed: 2010-05-25 - Assignees: Micron Technology, Inc. - Applicants: Eugene P. Marsh; Timothy A. Quick - Inventors: Eugene P. Marsh; Timothy A. Quick - Web page: https://patentgrep.com/patent/US8541765B2 ## CPC - H10N 70/021: {Formation of switching materials, e.g. deposition of layers} - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - H10N 70/023: {by chemical vapor deposition, e.g. MOCVD, ALD} - H10N 70/068: {by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers} - H10N 70/20: Multistable switching devices, e.g. memristors - H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect} - H10N 70/245: {the species being metal cations, e.g. programmable metallization cells} - H10N 70/8265: {on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices} - H10N 70/882: {Compounds of sulfur, selenium or tellurium, e.g. chalcogenides} - H10N 70/8822: {Sulfides, e.g. CuS} - H10N 70/8825: {Selenides, e.g. GeSe} - H10N 70/8828: {Tellurides, e.g. GeSbTe} - H10N 70/8833: {Binary metal oxides, e.g. TaOx} - H10N 70/884: {based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883)} - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Resistance variable memory cell structures and methods are described herein. One or more resistance variable memory cell structures include a first electrode common to a first and a second resistance variable memory cell, a first vertically oriented resistance variable material having an arcuate top surface in contact with a second electrode and a non-arcuate bottom surface in contact with the first electrode; and a second vertically oriented resistance variable material having an arcuate top surface in contact with a third electrode and a non-arcuate bottom surface in contact with the first electrode. ## Claims ### Claim 1 A method of forming a memory cell, comprising: forming a resistance variable memory cell material on a first electrode and a wall of a via; forming a first dielectric material on the resistance variable memory cell material; removing a portion of the first dielectric material such that a portion of the resistance variable memory cell material is exposed; forming a second electrode on a first exposed portion of the resistance variable memory cell material and third electrode on a second exposed portion of the resistance variable memory cell material; and forming a spacer material on at least a portion of the second electrode, the third electrode, and the first dielectric material. ### Claim 2 (depends on 1) The method of claim 1, wherein the method includes removing at least a portion of the spacer material between the second and third electrodes, at least a portion of the first dielectric material within the via, and at least a portion of the resistance variable memory cell material formed on the first electrode to form a first and a second resistance variable memory cell structure. ### Claim 3 (depends on 2) The method of claim 2, wherein forming the first and the second resistance variable memory cell structures includes forming a first arcuate resistance variable region corresponding to the first resistance variable memory cell structure and a second arcuate resistance variable region corresponding to the second resistance variable memory cell structure. ### Claim 4 (depends on 1) The method of claim 1, including forming the resistance variable memory cell material such that it has a thickness of no greater than 5 nanometers. ### Claim 5 (depends on 1) The method of claim 1, wherein forming the resistance variable memory cell material includes depositing the resistance variable memory cell material using atomic layer deposition. ### Claim 6 (depends on 1) The method of claim 1, wherein forming the resistance variable memory cell material includes depositing the resistance variable memory cell material using chemical vapor deposition. ### Claim 7 (depends on 1) The method of claim 1, including forming the first electrode of a material that is different than at least one of the second and the third electrode. ### Claim 8 (depends on 1) The method of claim 1, including forming the via through a second dielectric material to the first electrode prior to forming the resistance variable memory cell material on the first electrode and the wall of the via. ### Claim 9 (depends on 8) The method of claim 8, wherein removing the portion of the first dielectric material includes planarizing an upper surface of the semiconductor structure down to the second dielectric material. ### Claim 10 (depends on 1) The method of claim 1, including forming the second electrode and the third electrode such that a portion of each overlaps the first dielectric material formed in the via. ### Claim 11 A method of forming a memory cell, comprising: forming a memory cell structure having a via formed over a first electrode; forming a phase change material on the first electrode and on the walls of the via such that a gap remains between the walls of the via; forming a first dielectric material on the phase change material; removing a portion of the first dielectric material such that a portion of the phase change material is exposed and such that the first dielectric material remains only in the gap; forming a second electrode on a first exposed portion of the phase change material and third electrode on a second exposed portion of the phase change material; forming a spacer material on at least a portion of the second electrode, the third electrode, and the first dielectric material located in the gap; and removing at least a portion of the spacer material between the second and third electrodes, at least a portion of the first dielectric material within the via, and at least a portion of the phase change material formed on the first electrode such that a first and a second phase change memory cell structure is formed. ### Claim 12 (depends on 11) The method of claim 11, wherein removing the at least a portion of the spacer material between the second and third electrodes, the at least a portion of the first dielectric material within the via, and the at least a portion of the phase change material forms an arcuate phase change region corresponding to the first phase change memory cell structure and an arcuate phase change region corresponding to the second phase change memory cell structure, with the first electrode being common to the first and the second phase change memory cell structures. ### Claim 13 (depends on 11) The method of claim 11, wherein forming the first dielectric material includes depositing a low temperature oxide material. ### Claim 14 (depends on 11) The method of claim 11, including forming the second and third electrodes such that they overlap the dielectric material located in the gap. ### Claim 15 (depends on 11) The method of claim 11, including performing a dry etch to remove the at least a portion of the spacer material between the second and third electrodes, the at least a portion of the first dielectric material within the via, and the at least a portion of the phase change material formed on the first electrode. ### Claim 16 A resistance variable memory cell structure, comprising: a first electrode common to a first and a second resistance variable memory cell; a first vertically oriented resistance variable material having an arcuate top surface in contact with a second electrode and a non-arcuate bottom surface in contact with the first electrode; and a second vertically oriented resistance variable material having an arcuate top surface in contact with a third electrode and a non-arcuate bottom surface in contact with the first electrode; wherein the first electrode is made of a material different than at least one of the second and the third electrodes. ### Claim 17 (depends on 16) The resistance variable memory cell structure of claim 16, wherein an arcuate portion of the first and the second vertically oriented resistance variable material is located between a first dielectric material and a second dielectric material. ### Claim 18 (depends on 17) The resistance variable memory cell structure of claim 17, wherein the arcuate portion of the first vertically oriented resistance variable material is located a distance of not more than 20 nanometers from the arcuate portion of the second vertically oriented resistance variable material. ### Claim 19 (depends on 17) The resistance variable memory cell structure of claim 17, wherein the second electrode overlaps a portion of the first and the second dielectric material. ### Claim 20 (depends on 17) The resistance variable memory cell structure of claim 17, wherein a spacer material is formed on the first dielectric material and on an edge of the second electrode and an edge of the third electrode. ### Claim 21 (depends on 16) The resistance variable memory cell structure of claim 16, wherein the resistance variable material has a thickness of not greater than 5 nanometers. ### Claim 22 (depends on 16) The resistance variable memory cell structure of claim 16, wherein the second electrode is the top electrode of a first phase change memory cell, the third electrode is the top electrode of a second phase change memory cell, and the first electrode is a bottom electrode common to the first and second phase change memory cells. ### Claim 23 (depends on 16) The resistance variable memory cell structure of claim 16, wherein the arcuate top surface of the first and the second vertically oriented resistance variable material is a planarized surface. ### Claim 24 (depends on 16) The resistance variable memory cell structure of claim 16, wherein the first electrode is formed on a conductive contact. ### Claim 25 An array of resistance variable memory cells having at least a first and a second resistance variable memory cell structure formed according to a method, comprising: forming a memory cell structure having a via formed over a first electrode; forming a resistance variable memory cell material on the first electrode and a wall of the via; forming a first dielectric material on the resistance variable memory cell material; removing a portion of the first dielectric material such that a portion of the resistance variable memory cell material is exposed; forming a second electrode on a first exposed portion of the resistance variable memory cell material and third electrode on a second exposed portion of the resistance variable memory cell material; forming a spacer material on at least a portion of the second electrode, the third electrode, and the first dielectric material; and forming the first and the second resistance variable memory cell structure by removing at least a portion of the spacer material between the second and third electrodes, at least a portion of the first dielectric material within the via, and at least a portion of the resistance variable memory cell material formed on the first electrode. ### Claim 26 A method of forming a memory cell, comprising: forming a resistance variable memory cell material on a first electrode and a wall of a via such that the resistance variable memory cell material has a thickness of no greater than 5 nanometers; forming a first dielectric material on the resistance variable memory cell material; removing a portion of the first dielectric material such that a portion of the resistance variable memory cell material is exposed; and forming a second electrode on a first exposed portion of the resistance variable memory cell material and third electrode on a second exposed portion of the resistance variable memory cell material. ### Claim 27 A method of forming a memory cell, comprising: forming a resistance variable memory cell material on a first electrode and a wall of a via; forming a first dielectric material on the resistance variable memory cell material; removing a portion of the first dielectric material such that a portion of the resistance variable memory cell material is exposed; and forming a second electrode on a first exposed portion of the resistance variable memory cell material and third electrode on a second exposed portion of the resistance variable memory cell material; wherein the first electrode is formed of a material that is different than at least one of the second and the third electrode. ### Claim 28 A resistance variable memory cell structure, comprising: a first electrode common to a first and a second resistance variable memory cell; a first vertically oriented resistance variable material having an arcuate top surface in contact with a second electrode and a non-arcuate bottom surface in contact with the first electrode; and a second vertically oriented resistance variable material having an arcuate top surface in contact with a third electrode and a non-arcuate bottom surface in contact with the first electrode; wherein an arcuate portion of the first and the second vertically oriented resistance variable material is located between a first dielectric material and a second dielectric material; and wherein the arcuate portion of the first vertically oriented resistance variable material is located a distance of not more than 20 nanometers from the arcuate portion of the second vertically oriented resistance variable material. ### Claim 29 A resistance variable memory cell structure, comprising: a first electrode common to a first and a second resistance variable memory cell; a first vertically oriented resistance variable material having an arcuate top surface in contact with a second electrode and a non-arcuate bottom surface in contact with the first electrode; and a second vertically oriented resistance variable material having an arcuate top surface in contact with a third electrode and a non-arcuate bottom surface in contact with the first electrode; wherein an arcuate portion of the first and the second vertically oriented resistance variable material is located between a first dielectric material and a second dielectric material; and wherein a spacer material is formed on the first dielectric material and on an edge of the second electrode and an edge of the third electrode. ### Claim 30 A resistance variable memory cell structure, comprising: a first electrode common to a first and a second resistance variable memory cell; a first vertically oriented resistance variable material having an arcuate top surface in contact with a second electrode and a non-arcuate bottom surface in contact with the first electrode; and a second vertically oriented resistance variable material having an arcuate top surface in contact with a third electrode and a non-arcuate bottom surface in contact with the first electrode; wherein the first vertically oriented resistance variable material and the second vertically oriented resistance variable material have a thickness of not greater than 5 nanometers.