# US 8,541,757 B1 · Accelerator on a chip having a cold ion source

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- Number: US 8,541,757 B1
- Document ID: US8541757B1
- Status: Granted
- Kind: B1
- Application number: 13/585,829
- Filed: 2012-08-14
- Granted: 2013-09-24
- Earliest claimed: 2012-08-14
- Assignees: Transmute, Inc.
- Applicants: Kim L. Hailey; Robert O. Conn
- Inventors: Kim L. Hailey; Robert O. Conn
- Web page: https://patentgrep.com/patent/US8541757B1

## CPC

- H01J 37/3174: {Particle-beam lithography, e.g. electron beam lithography}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 40/00: Manufacture or treatment of nanostructures
- H01J 37/08: Ion sources; Ion guns
- H01J 37/09: Diaphragms; Shields associated with electron or ion-optical arrangements; Compensation of disturbing fields
- H01J 37/3177: {Multi-beam, e.g. fly's eye, comb probe}
- H01J 2237/0437: Semiconductor substrate
- H01J 2237/0802: Field ionization sources
- H01J 2237/31755: using ion beams
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

An assembly includes a cold ion source and a chip. The cold ion source is fixed to the chip so that ions from the ion source can enter an acceleration channel in the chip. In one specific example, the ion source includes an ion exchange membrane that produces cold ions in that the ions as produced have an energy of less than 30 eV. The chip includes a substrate (such as a semiconductor substrate or a glass substrate) and a dielectric layer disposed on substrate, where the acceleration channel is a channel formed into the dielectric layer. In one specific example, the assembly is part of a Direct Write On Wafer (DWOW) printing system. The DWOW printing system is useful in semiconductor processing in that it can direct write an image onto a 300 mm diameter wafer in one minute.

## Claims

### Claim 1

An accelerator assembly, comprising:
a chip, wherein an acceleration channel is formed in the chip; and
a cold ion source fixed to the chip so that ions from the cold ion source enter the acceleration channel.

### Claim 2 (depends on 1)

The accelerator assembly of claim 1, wherein the cold ion source generates the ions, and wherein the ions are generated by the cold ion source so that the ions have an energy less than 30 eV.

### Claim 3 (depends on 1)

The accelerator assembly of claim 1, wherein the cold ion source comprises an ion exchange membrane.

### Claim 4 (depends on 1)

The accelerator assembly of claim 1, wherein the cold ion source converts hydrogen gas into protons.

### Claim 5 (depends on 1)

The accelerator assembly of claim 1, wherein the chip comprises a semiconductor substrate.

### Claim 6 (depends on 1)

The accelerator assembly of claim 1, wherein the chip comprises:
a substrate taken from the group consisting of: a semiconductor substrate, a glass substrate, an alumina substrate, a sapphire substrate, a ceramic substrate; and
a dielectric layer disposed over the substrate.

### Claim 7 (depends on 1)

The accelerator assembly of claim 1, further comprising:
an amount of an adhesive that fixes the cold ion source to the chip.

### Claim 8 (depends on 1)

The accelerator assembly of claim 1, wherein the ions exit the acceleration channel having an energy of at least 1 KeV.

### Claim 9 (depends on 1)

The accelerator assembly of claim 1, wherein the acceleration channel has a length and a width, wherein the ratio of the length to the width is greater than five, and wherein the width is less than one micron.

### Claim 10 (depends on 1)

The accelerator assembly of claim 1, further comprising:
a Peltier cooler that is thermally coupled to the chip.

### Claim 11 (depends on 1)

The accelerator assembly of claim 1, wherein the ions are protons.

### Claim 12

A method, comprising:
(a) generating ions using a cold ion source, wherein the ions generated by the cold ion source have an energy less than 30 eV; and
(b) supplying the ions from the cold ion source into an acceleration channel, wherein the acceleration channel is a channel disposed in a chip, and wherein the cold ion source is fixed to the chip so that ions from the cold ion source enter the acceleration channel.

### Claim 13 (depends on 12)

The method of claim 12, wherein the cold ion source comprises an ion exchange membrane.

### Claim 14 (depends on 12)

The method of claim 12, wherein the chip comprises a substrate and a dielectric layer disposed over the substrate, wherein the substrate is taken from the group consisting of: a semiconductor substrate, a glass substrate, an alumina substrate, a sapphire substrate, a ceramic substrate.

### Claim 15 (depends on 14)

The method of claim 14, wherein acceleration channel has a length and a width, wherein the ratio of the length to the width is greater than five, and wherein the width is less than one micron.

### Claim 16 (depends on 12)

The method of claim 12, further comprising:
(c) accelerating the ions as they pass through the acceleration channel such that the ions have an energy of at least 1 KeV as they exit an ion exit port of the acceleration channel.