# US 8,541,690 B2 · Method for fixing an electronic component on a printed circuit board and system comprising a printed circuit board and at least one electronic component

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- Number: US 8,541,690 B2
- Document ID: US8541690B2
- Status: Granted
- Kind: B2
- Application number: 12/227,364
- Filed: 2007-05-15
- Published: 2009-04-23
- Granted: 2013-09-24
- Earliest claimed: 2006-05-16
- Assignees: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
- Applicants: Hannes Voraberger; Gerhard Schmid; Markus Riester; Johannes Stahr
- Inventors: Hannes Voraberger; Gerhard Schmid; Markus Riester; Johannes Stahr
- Web page: https://patentgrep.com/patent/US8541690B2

## CPC

- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H05K 1/113: {Via provided in pad; Pad over filled via}
- H05K 1/186: {manufactured by mounting on or connecting to patterned circuits before or during embedding}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/614: {the multiple chips being integrally enclosed}
- H05K 3/005: {Punching of holes}
- H05K 3/107: {by filling grooves in the support with conductive material (H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence)}
- H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)}
- H05K 3/465: {by applying an insulating layer having channels for the next circuit layer}
- H05K 3/4652: {Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern (H05K3/4647 takes precedence)}
- H05K 2201/09436: Pads or lands on permanent coating which covers the other conductors
- H05K 2201/10734: Ball grid array [BGA]; Bump grid array
- H10W 70/655: Fan-out layouts
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10T 29/4913: Assembling to base an electrical component, e.g., capacitor, etc.
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A method for fixing an electronic component on a printed circuit board, and contact-connecting the electronic component to the printed circuit board, the following steps are provided:—providing the printed circuit board having a plurality of contact and connection pads,—providing the electronic component having a number of contact and connection locations corresponding to the plurality of contact and connection pads, with a mutual spacing reduced in comparison with the spacing of the contact and connection pads, and—arranging or forming at least one interlayer for routing the contact and connection locations of the electronic component between the contact and connection pads and the contact and connection locations of the electronic component. A method for producing an interlayer for routing and a system having a printed circuit board and an electronic component using the interlayer for routing are also provided.

## Claims

### Claim 1

A process for attaching an electronic component on a circuit board or contacting the electronic component with the circuit board, comprising the steps of:
providing the circuit board with a plurality of contact or connection surfaces;
providing the electronic component with a number of contact or connection sites corresponding to the plurality of contact or connection surfaces of the circuit board, at mutual distances reduced relative to the distances of the contact or connection surfaces of the circuit board; and
forming between the contact or connection surfaces of the circuit board and the contact or connection sites of the electronic component at least one intermediate layer for disentangling the contact or connection sites of the electronic component;
wherein, after the structuring of the intermediate layer, an additional support layer for the attachment or contacting of the electronic component is applied on the intermediate layer for disentanglement and provided with contacts for the electronic component;
wherein the additional support layer covers both the intermediate layer and portions of the circuit board;
wherein the intermediate layer is merely formed in the region of the contact or connection surfaces of the circuit board as well as the contact or connection sites of the electronic component; and
wherein the intermediate layer is created as a part of a substrate of the circuit board by adding a layer to the circuit board.

### Claim 2 (depends on 1)

The process according to claim 1, wherein the intermediate layer is formed with conductive tracks or structures between contact zones corresponding to the contact or connection sites of the electronic component and corresponding to the contact or connection surfaces of the circuit board.

### Claim 3 (depends on 1)

The process according to claim 1, wherein contacting between the contact or connection sites of the electronic component and the intermediate layer is effected via contacts of the electronic component.

### Claim 4 (depends on 1)

The process according to claim 1, wherein contact or connection sites of the electronic component are directly contacted with contact zones of the intermediate layer.

### Claim 5 (depends on 1)

The process according to claim 1, wherein the electronic component is attached on the circuit board with contact or connection sites oriented away from the circuit board, and is overlaid by the intermediate layer for disentanglement and connection to the contact or connection surfaces of the circuit board.

### Claim 6

A process for producing an intermediate layer for disentangling contact or connection sites of an electronic component from contact or connection surfaces of a circuit board, comprising the steps of:
providing the circuit board with a plurality of contact or connection surfaces;
forming a base material of the intermediate layer merely in the region of the contact or connection surfaces of the circuit board;
structuring the intermediate layer to form conductive tracks or structures and contact sites for contacting with contact or connection surfaces of the circuit board and with contact or connection sites of an electronic component to be attached on the circuit board;
wherein, after the structuring of the intermediate layer, an additional support layer for the attachment or contacting of the electronic component is applied on the intermediate layer for disentanglement and provided with contacts for the electronic component;
wherein the additional support layer covers both the intermediate layer and portions of the circuit board; and
wherein the intermediate layer is created as a part of a substrate of the circuit board by adding a layer to the circuit board.

### Claim 7 (depends on 6)

The process according to claim 6, wherein the structuring of the intermediate layer is performed by subtractive techniques, semi-additive techniques, additive techniques or embossing techniques or laser structuring techniques.

### Claim 8 (depends on 6)

The process according to claim 6, wherein the intermediate layer is formed with a thickness reduced relative to the thickness of a circuit board layer.

### Claim 9 (depends on 8)

The process according to claim 8, wherein the thickness of the intermediate layer is selected to be less than half, in particular less than a third, of the thickness of a circuit board layer.

### Claim 10 (depends on 6)

The process according to claim 6, wherein the intermediate layer is provided with conductive tracks or conductive structures whose widths are selected to be less than 50 μm.

### Claim 11 (depends on 6)

The process according to claim 6, wherein the intermediate layer is used as a support or enclosure for the electronic component.

### Claim 12

A system including a circuit board and at least one electronic component, wherein at least one intermediate layer for the disentanglement of contact or connection sites of the electronic component from contact or connection surfaces of the circuit board is formed between the contact or connection sites of the electronic component and the contact or connection surfaces of the circuit board, and that the contact or connection sites of the electronic component comprise mutual distances reduced relative to the contact or connection sites of the circuit board; wherein an additional support layer for the attachment and contacting of the electronic component is applied on the intermediate layer for disentanglement and provided with contacts for the electronic component; wherein the intermediate layer is merely formed in the region of the contact or connection surfaces of the circuit board as well as the contact or connection sites of the electronic component; wherein the additional support layer covers both the intermediate layer and portions of the circuit board; and wherein the intermediate layer is created as part of a substrate of the circuit board by adding a layer to the circuit board.

### Claim 13 (depends on 12)

The system according to claim 12, wherein the intermediate layer is formed with conductive tracks or structures between contact zones corresponding to the contact or connection sites of the electronic component and corresponding to the contact or connection surfaces of the circuit board.

### Claim 14 (depends on 12)

The system according to claim 12, wherein the intermediate layer is formed with a thickness reduced relative to the thickness of a circuit board layer.

### Claim 15 (depends on 14)

The system according to claim 14, wherein the thickness of the intermediate layer amounts to less than half of the thickness of a circuit board layer.

### Claim 16 (depends on 12)

The system according to claim 12, wherein the intermediate layer is provided with conductive tracks or conductive structures whose widths are less than 50 μm.

### Claim 17 (depends on 12)

The system according to claim 12, wherein the intermediate layer is used as a support or enclosure for the electronic component.

### Claim 18 (depends on 12)

The system according to claim 12, wherein the circuit board is formed with a plurality of superimposed circuit board layers which are at least partially interconnected by conductive passages or microvias connecting individual circuit board layers.

### Claim 19 (depends on 6)

The process according to claim 6, wherein the intermediate layer is provided with conductive tracks or conductive structures whose widths are selected to be less than 30 μm.

### Claim 20 (depends on 14)

The system according to claim 14, wherein the thickness of the intermediate layer amounts to less than a third of the thickness of a circuit board layer.

### Claim 21 (depends on 12)

The system according to claim 12, wherein the intermediate layer is provided with conductive tracks or conductive structures whose widths are less than 30 μm.