# US 8,541,687 B2 · Coreless layer buildup structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,541,687 B2 - Document ID: US8541687B2 - Status: Granted - Kind: B2 - Application number: 12/764,993 - Filed: 2010-04-22 - Published: 2012-06-28 - Granted: 2013-09-24 - Earliest claimed: 2010-04-22 - Assignees: Endicott Interconnect Technologies, Inc. - Applicants: Voya Markovich; Timothy Antesberger; Frank D. Egitto; William Wilson; Rabindra N. Das - Inventors: Voya Markovich; Timothy Antesberger; Frank D. Egitto; William Wilson; Rabindra N. Das - Web page: https://patentgrep.com/patent/US8541687B2 ## CPC - H05K 3/462: {characterized by laminating only or mainly similar double-sided circuit boards} - H05K 1/167: {incorporating printed resistors} - H05K 3/4069: {for via connections in organic insulating substrates} - H05K 3/4623: {the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards (H05K3/462 takes precedence)} - H05K 3/4632: {laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets} - H05K 2203/0191: Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste - H05K 2203/061: of previously made multilayered subassemblies - H05K 2203/063: of preperforated insulating layer - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. ## Claims ### Claim 1 A coreless substrate for use in a PC board comprising: a) an etched first metal layer having a first and a second surface; b) at least two coreless, partially-filled thermoset resin-coated CU-based buildup layers disposed respectively on said first and said second surfaces; c) a second and a third metal layer disposed on said at least two coreless buildup layers, respectively; and d) an electrical connection between said first and said second metal layers, and said first and said third metal layers, and said second and said third metal layers; whereby a high density, thin, coreless substrate is produced. ### Claim 2 (depends on 1) The coreless substrate as per claim 1, wherein said at least two coreless buildup layers comprise a partially-cured fiberglass cloth-impregnated, filled thermoset resin. ### Claim 3 (depends on 1) The coreless substrate as per claim 1, wherein said at least two coreless buildup layers comprise a thermoplastic resin. ### Claim 4 (depends on 2) The coreless substrate as per claim 2, wherein said at least two coreless buildup layers comprise alternate layers of partially-cured and fully-cured resin. ### Claim 5 (depends on 1) The coreless substrate as per claim 1, further comprising: e) a first joining layer of dielectric disposed between said first and said second metal layers. ### Claim 6 (depends on 5) The coreless substrate as per claim 5, wherein said first and said second metal layers each comprises two to six metal layers. ### Claim 7 (depends on 5) The coreless substrate as per claim 5, wherein said first joining layer of dielectric comprises at least one from the group: partially-cured thermoset resin and thermoplastic. ### Claim 8 (depends on 5) The coreless substrate as per claim 5, wherein said first joining layer of dielectric comprises at least one from the group: high dielectric constant and low loss capacitance material. ### Claim 9 (depends on 5) The coreless substrate as per claim 5, wherein said first and said second metal layers comprise resistor foil laminated and circuitized on at least one from the group: at least partially-cured thermoset and thermoplastic resin dielectric layer. ### Claim 10 (depends on 6) The coreless substrate as per claim 6, wherein said first and said second metal layers comprise a multilayer resistor foil. ### Claim 11 (depends on 10) The coreless substrate as per claim 10, wherein said multilayer resistor foil comprises a resistance range of 15 ohms to 30,000 ohms. ### Claim 12 (depends on 9) The coreless substrate as per claim 9, wherein said multilayer resistor foil comprises at least one from the group: high dielectric constant and low loss capacitance layer. ### Claim 13 (depends on 5) The coreless substrate as per claim 5, further comprising; f) a third metal layer. ### Claim 14 (depends on 13) The coreless substrate as per claim 13, further comprising: g) a second joining layer of dielectric disposed between said second and said third metal layers. ### Claim 15 (depends on 14) The coreless substrate as per claim 14, wherein said second joining layer of dielectric comprises capacitance material. ### Claim 16 (depends on 13) The coreless substrate as per claim 13, wherein said first and said second and said third metal layers comprise at least one from the group: signal, power, and ground. ### Claim 17 (depends on 13) The coreless substrate as per claim 13, further comprising conductive paste comprising at least one set of metal micro particles chosen from the group: copper, silver, gold, zinc, cadmium, palladium, iridium, ruthenium, osmium, rhodium, platinum, iron, cobalt, nickel, indium, tin, antimony, lead, bismuth and alloys thereof. ### Claim 18 (depends on 17) The coreless substrate as per claim 17, wherein the decomposition temperature of said conductive paste is approximately 340° C.