# US 8,541,308 B2 · Polishing method and method for forming a gate

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- Number: US 8,541,308 B2
- Document ID: US8541308B2
- Status: Granted
- Kind: B2
- Application number: 13/244,196
- Filed: 2011-09-23
- Published: 2012-10-25
- Granted: 2013-09-24
- Earliest claimed: 2011-04-20
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Li Jiang; Mingqi Li
- Inventors: Li Jiang; Mingqi Li
- Web page: https://patentgrep.com/patent/US8541308B2

## CPC

- H10P 95/062: {involving a dielectric removal step}
- C09G 1/04: Aqueous dispersions (C09G1/02 takes precedence)
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- C09G: POLISHING COMPOSITIONS (French polish C09F11/00); SKI WAXES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A polishing method and a method for forming a gate are provided. The method includes forming a dummy gate on a semiconductor substrate including a sacrificial oxide layer and a polysilicon layer which covers the sacrificial oxide layer, forming spacers around the dummy gate, and successively forming a silicon nitride layer and a dielectric layer covering the silicon nitride layer. The method further includes polishing the dielectric layer until the silicon nitride layer is exposed, polishing the silicon nitride layer on a fixed abrasive pad until the polysilicon layer is exposed by using a polishing slurry with a PH value ranging from 10.5 to 11 and comprising an anionic surfactant or a zwitterionic surfactant. Additionally, the method includes forming an opening after removing the dummy gate, and forming a gate in the opening. The method eliminates potential erosion and dishing caused in the polishing of the silicon nitride layer.

## Claims

### Claim 1

A polishing method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate includes a polysilicon layer, a silicon nitride layer overlying the polysilicon layer, and a dielectric layer overlying the silicon nitride layer;
polishing the dielectric layer until the silicon nitride layer is exposed; and
polishing the silicon nitride layer by a fixed abrasive pad having an abrasive thereon until the polysilicon layer is exposed, wherein a polishing slurry used in the polishing process is featured with a PH value ranging from 10.5 to 11, and comprising an anionic surfactant or a zwitterionic surfactant, wherein the dielectric layer comprising silicon dioxide is polished using the polishing slurry, and wherein a removal rate of the polysilicon layer by the polishing slurry is less than about 50 Å/min.

### Claim 2 (depends on 1)

The polishing method according to claim 1, wherein the zwitterionic surfactant comprises proline.

### Claim 3 (depends on 1)

The polishing method according to claim 1, wherein abrasive on the fixed abrasive pad comprises cerium oxide.

### Claim 4 (depends on 1)

The polishing method according to claim 1, wherein the polishing the silicon nitride layer comprises a pressure having an intensity ranging from 1 to 2 psi and a rotational speed of a polishing platen ranging from 10 to 25 rpm.

### Claim 5 (depends on 1)

The polishing method according to claim 1, wherein the polishing comprises an endpoint detection method.

### Claim 6 (depends on 5)

The polishing method according to claim 5, wherein the endpoint detection method comprises a motor current endpoint detection or an optics endpoint detection.

### Claim 7

A method for forming a gate, the method comprising:
forming a dummy gate on a semiconductor substrate, wherein the dummy gate comprises a sacrificial oxide layer and a polysilicon layer overlying the sacrificial oxide layer;
forming spacers around the dummy gate;
successively forming a silicon nitride layer and a dielectric layer overlying the silicon nitride layer, wherein the silicon nitride layer covers the polysilicon layer, the spacers, and the semiconductor substrate;
polishing the dielectric layer until the silicon nitride layer is exposed;
polishing the silicon nitride layer by a fixed abrasive pad until the polysilicon layer is exposed, wherein a polishing slurry used in the polishing process is featured with a PH value ranging from 10.5 to 11 and comprising an anionic surfactant or a zwitterionic surfactant, wherein the dielectric layer comprising silicon dioxide is polished using the polishing slurry, and wherein a removal rate of the polysilicon layer by the polishing slurry is less than about 50 Å/min;
forming an opening after removing the dummy gate; and
forming a gate in the opening.

### Claim 8 (depends on 7)

The method for forming a gate according to claim 7, wherein the zwitterionic surfactant comprises proline.

### Claim 9 (depends on 7)

The method for forming a gate according to claim 7, wherein the fixed abrasive pad comprises an abrasive including cerium oxide.

### Claim 10 (depends on 7)

The method for forming a gate according to claim 7, wherein the polishing the silicon nitride layer comprises a pressure intensity ranging from 1 to 2 psi and a rotational speed of a polishing platen ranging from 10 to 25 rpm.

### Claim 11 (depends on 7)

The method for forming a gate according to claim 7, wherein polishing the dielectric layer comprises a fixed abrasive pad or an unfixed abrasive pad.