# US 8,541,305 B2 · 3D integrated circuit and method of manufacturing the same

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- Number: US 8,541,305 B2
- Document ID: US8541305B2
- Status: Granted
- Kind: B2
- Application number: 13/003,744
- Filed: 2010-09-19
- Published: 2011-11-24
- Granted: 2013-09-24
- Earliest claimed: 2010-05-24
- Assignees: Institute of Microelectronics, Chinese Academy of Sciences
- Applicants: Huilong Zhu
- Inventors: Huilong Zhu
- Web page: https://patentgrep.com/patent/US8541305B2

## CPC

- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a 3D integrated circuit and a manufacturing method thereof. The circuit structure comprises: a semiconductor substrate; at least one semiconductor device formed on the upper surface of the semiconductor substrate; a through-Si-via through the semiconductor substrate and comprising an insulating layer covering sidewalls of the through-Si-via and conductive material filled in the insulating layer; an interconnection structure connecting the at least one semiconductor device and the through-Si-via; and a diffusion trapping region formed on the lower surface of the semiconductor substrate. The present invention is applicable in manufacture of the 3D integrated circuit.

## Claims

### Claim 1

A three-dimensional integrated circuit structure, comprising:
a semiconductor substrate;
at least one semiconductor device formed on the upper surface of the semiconductor substrate;
a through-Si-via extending through the semiconductor substrate, and comprising a conductive via and an insulating layer covering sidewalls of the conductive via;
an interconnection structure connecting the at least one semiconductor device and the through-Si-via; and
a diffusion trapping region formed on the lower surface of the semiconductor substrate and surrounding the through-Si-via.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the diffusion trapping region comprises any one or more ions of Ar, Xe, Ge, and P.

### Claim 3 (depends on 1)

The structure of claim 1, wherein an implantation depth in the diffusion trapping region is in the range of about 10-1000 nm.

### Claim 4 (depends on 1)

The structure of claim 1, wherein an implantation dose of ions in the diffusion trapping region is in the range of about 1013-1016/cm2.

### Claim 5 (depends on 1)

The structure of claim 1, wherein the diffusion trapping region is a trapping region for metal ions.

### Claim 6 (depends on 1)

The structure of claim 1, wherein the diffusion trapping region is formed at the lower surface of the semiconductor substrate by self-aligning the outer periphery of the through-Si-via.

### Claim 7

A manufacturing method of a 3D integrated circuit, comprising:
providing a semiconductor substrate with at least one semiconductor device formed on an upper surface of the semiconductor substrate;
forming a through-Si-via in the semiconductor substrate, wherein the through-Si-via comprises a conductive via and an insulating layer covering sidewalls of the conductive via;
forming an interconnection structure connecting the at least one semiconductor device and the through-Si-via;
selectively etching a lower surface of the semiconductor substrate to stop at the insulating layer of the through-Si-via;
forming a diffusion trapping region on the etched lower surface; and
removing a part of the through-Si-via higher than the lower surface.

### Claim 8 (depends on 7)

The method of claim 7, further comprising depositing a protection layer on the lower surface after forming the diffusion trapping region, and selectively removing the protection layer at the same time when removing the part of the through-Si-via higher than the lower surface.

### Claim 9 (depends on 7)

The method of claim 7, wherein forming the diffusion trapping region on the lower surface comprises forming the diffusion trapping region by self-aligning the outer periphery of the through-Si-via.

### Claim 10 (depends on 7)

The method of claim 7, wherein forming the diffusion trapping region comprises implanting ions into the lower surface, and the implanted ions comprise any one or more of Ar, Xe, Ge, and P.

### Claim 11 (depends on 10)

The method of claim 10, wherein the depth for the ions implantation is controlled to be in the range of about 10-1000 nm.

### Claim 12 (depends on 10)

The method of claim 10, wherein the implantation dose of the ions is in the range of about 1013-1016/cm2.

### Claim 13 (depends on 7)

The method of claim 7, further comprises the lower surface of the semiconductor substrate being grinded to be thinned before selectively etching the lower surface.

### Claim 14 (depends on 7)

The method of claim 7, wherein the diffusion trapping region is a trapping region for metal ions.

### Claim 15 (depends on 8)

The method of claim 8, wherein the diffusion trapping region is a trapping region for metal ions.

### Claim 16 (depends on 9)

The method of claim 9, wherein the diffusion trapping region is a trapping region for metal ions.

### Claim 17 (depends on 10)

The method of claim 10, wherein the diffusion trapping region is a trapping region for metal ions.

### Claim 18 (depends on 2)

The structure of claim 2, wherein the diffusion trapping region is formed at the lower surface of the semiconductor substrate by self-aligning the outer periphery of the through-Si-via.

### Claim 19 (depends on 3)

The structure of claim 3, wherein the diffusion trapping region is formed at the lower surface of the semiconductor substrate by self-aligning the outer periphery of the through-Si-via.

### Claim 20 (depends on 4)

The structure of claim 4, wherein the diffusion trapping region is formed at the lower surface of the semiconductor substrate by self-aligning the outer periphery of the through-Si-via.