# US 8,541,302 B2 · Electronic device including a trench with a facet and a conductive structure therein and a process of forming the same

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- Number: US 8,541,302 B2
- Document ID: US8541302B2
- Status: Granted
- Kind: B2
- Application number: 13/327,454
- Filed: 2011-12-15
- Published: 2013-06-20
- Granted: 2013-09-24
- Earliest claimed: 2011-12-15
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Gary H. Loechelt; Gordon M. Grivna
- Inventors: Gary H. Loechelt; Gordon M. Grivna
- Web page: https://patentgrep.com/patent/US8541302B2

## CPC

- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0293: {using formation of insulating sidewall spacers}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 64/01: Manufacture or treatment
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10P 50/242: {of Group IV materials}
- H10P 50/694: {characterised by their behaviour during the process, e.g. soluble masks or redeposited masks}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/111: {Field plates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic device can include a transistor structure including a semiconductor layer overlying a substrate and a trench extending into the semiconductor layer having a tapered shape. In an embodiment, the tapered shape includes a facet. The transistor structure can include a source region and a drain region wherein different portions of the drain regions are disposed adjacent to the primary surface and within the trench. In another embodiment, different facets may be spaced apart from each other. Processes of forming the tapered etch can be tailored based on the needs or desires of a fabricator.

## Claims

### Claim 1

An electronic device comprising a transistor structure, comprising:
a semiconductor layer overlying a substrate and having a primary surface that generally corresponds to a first plane;
a trench extending into the semiconductor layer having a tapered shape, wherein the tapered shape includes a facet that lies substantially along a second plane that intersects the first plane at an angle in a range of approximately 20° to approximately 70°;
a source region of the transistor structure; and
a drain region of the transistor structure,
wherein:
portions of the source and drain regions are disposed adjacent to the primary surface; and
another portion of the drain region is disposed within the trench.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein the transistor structure comprises:
a channel region disposed between the source and drain regions, wherein the channel region is disposed along the primary surface of the semiconductor layer; and
a gate electrode overlying the channel region, wherein substantially all of the gate electrode is disposed at an elevation above the primary surface.

### Claim 3 (depends on 1)

The electronic device of claim 1, wherein the drain region comprises:
a doped semiconductor region adjacent to a tapered portion of the trench, wherein a dopant concentration of the doped semiconductor region is greater than a dopant concentration of the semiconductor layer at a location adjacent to the primary surface; and
a conductive structure disposed within another portion of the trench below the tapered portion, wherein the other portion has a substantially vertical sidewall.

### Claim 4 (depends on 3)

The electronic device of claim 3, further comprising an underlying doped region and a drain terminal, wherein:
the semiconductor layer is disposed over the underlying doped region;
the conductive structure is electrically connected to the doped semiconductor region and the underlying doped region; and
the underlying doped region is coupled to the drain terminal.

### Claim 5

An electronic device comprising:
a semiconductor layer overlying a substrate and having a primary surface; and
a trench extending into the semiconductor layer and having a first facet and a second facet spaced apart from the second facet, wherein:
the first facet is disposed closer to the primary surface as compared to the second facet;
the first facet lies along a first plane, the second facet lies along a second plane, and the primary surface generally corresponds to a third plane; and
each of the first and second planes intersects the third plane at an angle in a range of approximately 20° to approximately 70°.

### Claim 6 (depends on 5)

The electronic device of claim 5, wherein substantially all of the first facet is disposed at an elevation higher than substantially all of the second facet.

### Claim 7 (depends on 5)

The electronic device of claim 5, wherein the trench has a substantially vertical sidewall between the first and second facets.

### Claim 8 (depends on 7)

The electronic device of claim 7, further comprising another substantially vertical sidewall disposed below the second facet.

### Claim 9 (depends on 7)

The electronic device of claim 7, further comprising:
a doped semiconductor region including a first portion adjacent to the first facet and a second portion adjacent to the second facet, wherein a dopant concentration of the doped semiconductor region is greater than a dopant concentration of the semiconductor layer at a location adjacent to the primary surface; and
a conductive electrode extending into the trench such that a lowest elevation of the conductive electrode within the trench is below a highest elevation of the second facet.

### Claim 10 (depends on 9)

The electronic device of claim 9, further comprising:
a first insulating layer disposed between the first portion of the doped semiconductor region and the conductive electrode; and
a second insulating layer disposed between the second portion of the doped semiconductor region and the conductive electrode, wherein the second insulating layer is thicker than the first insulating layer.

### Claim 11

A process of forming an electronic device comprising:
providing a semiconductor layer overlying a substrate and having a primary surface that generally corresponds to a first plane;
patterning a semiconductor layer to define a trench; and
forming a facet from a portion of the semiconductor layer, wherein the facet lies along a second plane that intersects the first plane at an angle in a range of approximately 20° to approximately 70°,
wherein in a finished device:
the facet is spaced apart from a bottom of the trench; and
as compared to a bottom of the trench, a lowest elevation of the facet is disposed closer to the primary surface.

### Claim 12 (depends on 11)

The process of claim 11, wherein forming the facet comprises sputter etching the semiconductor layer.

### Claim 13 (depends on 11)

The process of claim 11, further comprising forming a patterned resist layer over the semiconductor layer, wherein forming the facet comprises:
anisotropically etching the semiconductor layer; and
eroding the resist layer during anisotropically etching the semiconductor layer.

### Claim 14 (depends on 11)

The process of claim 11, wherein forming the facet comprises wet etching the semiconductor layer with an etchant that preferentially etches along a crystal plane that is within approximately 10° of the second plane.

### Claim 15 (depends on 14)

The process of claim 14, wherein the etchant comprises a hydroxide and an alcohol.

### Claim 16 (depends on 11)

The process of claim 11, wherein forming the facet is performed after patterning the semiconductor layer.

### Claim 17 (depends on 11)

The process of claim 11, wherein patterning the semiconductor layer is performed after forming the facet.