# US 8,541,298 B2 · Method for fabricating semiconductor device

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- Number: US 8,541,298 B2
- Document ID: US8541298B2
- Status: Granted
- Kind: B2
- Application number: 13/185,002
- Filed: 2011-07-18
- Published: 2012-01-26
- Granted: 2013-09-24
- Earliest claimed: 2010-07-21
- Assignees: Sumitomo Electric Device Innovations, Inc.
- Applicants: Hiroshi Kawakubo
- Inventors: Hiroshi Kawakubo
- Web page: https://patentgrep.com/patent/US8541298B2

## CPC

- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10P 50/242: {of Group IV materials}
- H10P 50/246: {of Group III-V materials}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10D 62/8325: {Silicon carbide}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for fabricating a semiconductor device having a GaN-based semiconductor layer on a first surface of a substrate made of SiC, a pad being provided on the GaN-based layer, includes: forming a first via hole in the substrate by etching, with fluorine based gas, from a second surface of the substrate opposite to the first surface, the etching being carried out with the GaN-based layer being used as an etch stopper; and forming a second via hole in the GaN-based semiconductor layer, with chlorine based gas, from a bottom surface of the first via hole, the etching being carried out with the pad being used as an etching stopper, the chlorine based gas being an etchant different from the fluorine based gas.

## Claims

### Claim 1

A method for fabricating a semiconductor device having a GaN-based semiconductor layer on a first surface of a substrate made of SiC, a pad being provided on the GaN-based layer, comprising:
forming a first via hole in the substrate by etching, with fluorine based gas, from a second surface of the substrate opposite to the first surface, the etching being carried out with the GaN-based layer being used as an etch stopper; and
forming a second via hole in the GaN-based semiconductor layer, with chlorine based gas, from a bottom surface of the first via hole, the etching being carried out with the pad being used as an etching stopper, the chlorine based gas being an etchant different from the fluorine based gas,
wherein the forming of the first via hole includes etching with a mask layer that is formed on the second surface of the substrate, and the mask includes any of Cu, Ni and Pt, and the forming of the second via hole is carried out by etching with the substrate being used as a mask;
removing the mask used in the forming of the first via hole before carrying out the forming of the second via hole.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the forming of the first via hole and the forming of the second via hole uses any of inductively coupled plasma etching, transformer coupled plasma etching and reactive ion etching, and wherein an antenna power in etching is 2500 W to 5000 W, and a bias power is 300 W to 500 W.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the fluorine based gas includes SF6.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the chlorine based gas includes one of Cl2, SiCl4 and BCl3.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the substrate has a thickness of 50 μm to 150 μm.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the pad includes Ni.

### Claim 7 (depends on 6)

The method according to claim 6, wherein the pad is composed of Ni and Au on the GaN-based semiconductor layer in this order.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the GaN-based semiconductor layer includes at least one of GaN, InGaN, AlGaN and InAlGaN.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the GaN-based semiconductor layer is composed of a GaN layer, an AlGaN layer, and a GaN layer on the substrate in this order.

### Claim 10 (depends on 1)

The method according to claim 1, further comprising forming a metal layer on the second surface of the substrate and inner surfaces of the first and second via-holes.

### Claim 11 (depends on 10)

The method according to claim 10, wherein the metal layer comprises Ni and Au on the second surface of the substrate and the inner surfaces of the first and second via-holes in this order.

### Claim 12

A method for forming a via-hole in a stacked structure of a SiC substrate and a GaN-based semiconductor layer, comprising:
forming a pad layer on the GaN-based semiconductor layer;
forming a mask on a back side surface of the substrate opposite to the GaN-based semiconductor layer;
forming a via-hole by etching the substrate from a side of the back side surface by using an etchant of fluorine based gas and etching the GaN-based semiconductor layer from the side of the back side surface by using an etchant of chlorine based gas which has a composition different from that of the fluorine based gas; and
removing the mask before etching the GaN-based semiconductor layer.

### Claim 13 (depends on 12)

The method according to claim 12, wherein after removing the mask, the etching of the GaN-based semiconductor layer uses the SiC substrate as a mask.

### Claim 14 (depends on 13)

The method according to claim 13, wherein the mask formed on the back side surface of the SiC substrate includes one of Cu, Ni and Pt.

### Claim 15 (depends on 13)

The method according to claim 13, wherein the GaN-based semiconductor layer includes at least one of GaN, InGaN, AlGaN and InAlGaN.