# US 8,541,296 B2 · Method of manufacturing dummy gates in gate last process

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- Number: US 8,541,296 B2
- Document ID: US8541296B2
- Status: Granted
- Kind: B2
- Application number: 13/510,730
- Filed: 2011-11-30
- Published: 2013-03-07
- Granted: 2013-09-24
- Earliest claimed: 2011-09-01
- Assignees: The Institute of Microelectronics Chinese Academy of Science
- Applicants: Tao Yang; Chao Zhao; Jiang Yan; Junfeng Li; Yihong Lu; Dapeng Chen
- Inventors: Tao Yang; Chao Zhao; Jiang Yan; Junfeng Li; Yihong Lu; Dapeng Chen
- Web page: https://patentgrep.com/patent/US8541296B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/68: characterised by the insulator, e.g. by the gate insulator
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/283: {by chemical means}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.

## Claims

### Claim 1

A method of manufacturing a dummy gate in a gate last process, which comprises the following steps:
forming a dummy gate material layer and a hard mask material layer sequentially on a substrate;
etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; and
dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate,
wherein the hard mask material layer comprises a first mask layer and a second mask layer located on the first mask layer, and
wherein the top-wide-bottom-narrow hard mask pattern is formed by wet etching the hard mask material layer in a single step with wet etching solution, which etches the first mask layer faster than etches the second mask layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein a hard mask pattern with vertical sidewalls is formed first by dry etching, then the first mask layer is wet etched to form the top-wide-bottom-narrow hard mask pattern.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the first mask layer and the second mask layer comprise silicon oxide, silicon nitride and/or silicon oxynitride.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the dummy gate material layer comprises polycrystalline silicon, amorphous silicon, or microcrystal silicon, and the substrate comprises bulk silicon, SOI, monocrystalline germanium, GeOI, SiGe, SiC, InSb, GaAs or GaN.

### Claim 5 (depends on 1)

A gate last process, which comprises the steps of:
forming a top-wide-bottom-narrow dummy gate on a substrate using the method of manufacturing a dummy gate in a gate last process as claimed in claim 1;
forming sidewall spacers on both sides of the dummy gate;
removing the dummy gate to form a top-wide-bottom-narrow gate trench; and
filling the gate trench with a gate insulation layer and a gate material.

### Claim 6 (depends on 1)

The method according to claim 1, wherein etching solution for the wet etching includes DHF, BOE, hot phosphoric acid or H2O2.

### Claim 7 (depends on 2)

The method according to claim 2, wherein in the formed top-wide-bottom-narrow hard mask pattern, the second mask layer has an over-hang portion beyond the first mask layer.

### Claim 8 (depends on 2)

The method according to claim 2, wherein etching solution for the wet etching includes DHF, BOE, hot phosphoric acid or H2O2.

### Claim 9 (depends on 7)

The method according to claim 7, wherein the width of the over-hang portion and the thickness of the dummy gate material layer are adjusted to control an angle of inclination of the dummy gate.