# US 8,541,295 B2 · Pad-less gate-all around semiconductor nanowire FETs on bulk semiconductor wafers

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- Number: US 8,541,295 B2
- Document ID: US8541295B2
- Status: Granted
- Kind: B2
- Application number: 13/759,641
- Filed: 2013-02-05
- Published: 2013-08-29
- Granted: 2013-09-24
- Earliest claimed: 2012-02-27
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Jeffrey W. Sleight; Josephine B. Chang; Isaac Laurer; Shreesh Narasimha
- Web page: https://patentgrep.com/patent/US8541295B2

## CPC

- H10D 30/021: {of FETs having insulated gates [IGFET]}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/435: {having multiple laterally adjacent 1D material channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- B82Y 40/00: Manufacture or treatment of nanostructures
- Y10S 977/762: Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A non-planar semiconductor device is provided including at least one semiconductor nanowire suspended above a semiconductor oxide layer present within a portion of a bulk semiconductor substrate. The semiconductor oxide layer has a topmost surface that is coplanar with a topmost surface of the bulk semiconductor substrate. A gate surrounds a portion of the at least one suspended semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate. The source region is in direct contact with an exposed end portion of the at least one suspended semiconductor nanowire, and the drain region is in direct contact with another exposed end portion of the at least one suspended semiconductor nanowire. The source and drain regions have an epitaxial relationship with the exposed end portions of the suspended semiconductor nanowire.

## Claims

### Claim 1

A method of forming a non-planar semiconductor device comprising:
forming at least one semiconductor wire region within a bulk semiconductor substrate;
providing a sacrificial spacer to vertical sidewalls of said at least one semiconductor wire region;
removing portions of the bulk semiconductor substrate to provide an undercut beneath the sacrificial spacer and a vertical semiconductor pillar portion directly beneath the at least one semiconductor wire region;
performing an oxidation process converting a recessed surface of the bulk semiconductor substrate into a horizontal semiconductor oxide portion, and converting the vertical semiconductor pillar portion into a vertical semiconductor oxide pillar portion;
removing at least said vertical semiconductor oxide pillar portion and said sacrificial spacer forming at least one suspended semiconductor nanowire, while retaining at least a portion of said horizontal semiconductor oxide portion on said recessed surface of said semiconductor substrate, wherein said at least one suspended semiconductor nanowire has an end segment attached to a first semiconductor pad region and another end segment attached to a second semiconductor pad region, said first and second semiconductor pad regions are located above and are in direct contact with a non-recessed portion of the bulk semiconductor substrate;
performing a hydrogen anneal on said at least one suspended semiconductor nanowire;
providing a gate surrounding a central portion of said at least one suspended semiconductor nanowire;
forming a spacer on opposing sides of said gate and covering a portion of said at least one suspended semiconductor nanowire;
removing exposed portions of the at least one suspended semiconductor nanowire and said first and second semiconductor pad regions to provide at least one cut semiconductor nanowire having exposed end portions; and
forming a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite said first side of the gate.

### Claim 2 (depends on 1)

The method of claim 1, wherein said removing exposed portions of the at least one suspended semiconductor nanowire and said first and second semiconductor pad regions comprises a selective reactive ion etching process.

### Claim 3 (depends on 2)

The method of claim 2, wherein said selective reactive ion etching process comprises HBr chemistry.

### Claim 4 (depends on 1)

The method of claim 1, wherein said forming the source region and the drain region comprises epitaxially growing a semiconductor material from said exposed end portions of the at least one cut semiconductor nanowire.

### Claim 5 (depends on 1)

The method of claim 1, further comprising forming a metal semiconductor alloy material located atop said source region and said drain region.

### Claim 6 (depends on 1)

The method of claim 1, wherein said hydrogen anneal provides at least one elliptical shaped suspended semiconductor nanowire.

### Claim 7 (depends on 1)

The method of claim 1, wherein said hydrogen anneal provides at least one cylindrical shaped suspended semiconductor nanowire.

### Claim 8 (depends on 1)

The method of claim 1, further comprising forming a polysilicon line atop the gate prior to forming said spacer.

### Claim 9 (depends on 8)

The method of claim 8, further comprising forming a metal semiconductor alloy atop said polysilicon line.

### Claim 10 (depends on 1)

The method of claim 1, wherein said removing portions of the bulk semiconductor substrate to provide said undercut and said vertical semiconductor pillar portion comprises a recess etch.

### Claim 11 (depends on 1)

The method of claim 1, wherein said removing at least said vertical semiconductor oxide pillar portion beneath the at least one semiconductor wire region comprises an anisotropic etch.

### Claim 12 (depends on 1)

The method of claim 1, further comprising thinning said at least one suspended semiconductor nanowire after performing said hydrogen anneal.

### Claim 13 (depends on 12)

The method of claim 12, wherein said thinning comprises oxidation, followed by etching.

### Claim 14 (depends on 1)

The method of claim 1, wherein said forming the gate comprises forming a first gate dielectric material and forming a second gate dielectric material.

### Claim 15 (depends on 14)

The method of claim 14, wherein said forming the gate further comprises forming a metal gate film on a surface of the second gate dielectric material.