# US 8,541,288 B2 · Manufacturing method of thin film transistor array substrate

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- Number: US 8,541,288 B2
- Document ID: US8541288B2
- Status: Granted
- Kind: B2
- Application number: 13/775,270
- Filed: 2013-02-25
- Published: 2013-06-27
- Granted: 2013-09-24
- Earliest claimed: 2011-01-28
- Assignees: Chunghwa Picture Tubes, Ltd.
- Applicants: Chunghwa Picture Tubes, Ltd.
- Inventors: Der-Chun Wu; Yu-Hsien Chen; Sheng-Fa Liu
- Web page: https://patentgrep.com/patent/US8541288B2

## CPC

- G02F 1/133784: {by rubbing}
- G02F 1/133707: {Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes}
- H10P 14/60: of insulating materials
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/301: {for alignment}
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A manufacturing method for a TFT array substrate includes providing a substrate; defining a plurality of normal alignment regions and a plurality of abnormal alignment regions on the substrate; forming an insulating layer and a transparent conductive layer on the substrate; performing a patterning process to at least one of the insulating layer and the transparent conductive layer to form a plurality of alignment structures in each abnormal alignment region; forming an alignment material layer on the substrate, the alignment material layer having a plurality of first alignment slits formed along the alignment structures in each of the abnormal alignment regions; and performing a rubbing alignment process to form a plurality of second alignment slits on the alignment material layer in each of the normal alignment regions along a alignment direction.

## Claims

### Claim 1

A manufacturing method for a thin film transistor (TFT) array substrate, comprising:
providing a substrate having a plurality of scan lines, a plurality of data lines, a plurality of storage electrode lines, and a plurality of switch devices formed thereon;
defining a plurality of normal alignment regions and a plurality of abnormal alignment regions on the substrate; wherein the normal alignment regions are defined at sides of the scan lines, the data lines, the storage electrode line, and the switch devices, and the abnormal alignment regions are defined at opposite sides of the scan lines, the data lines, the storage electrode lines, and the switch devices;
forming an insulating layer and a transparent conductive layer on the substrate, sequentially;
performing a patterning process to at least one of the insulating layer and the transparent conductive layer to form a plurality of alignment structures in each abnormal alignment region;
forming an alignment material layer on the substrate, the alignment material layer having a plurality of first alignment slits formed along the alignment structures in each of the abnormal alignment regions; and
performing a rubbing alignment process to form a plurality of second alignment slits in the alignment material layer in each of the normal alignment regions along an alignment direction.

### Claim 2 (depends on 1)

The manufacturing method for a TFT array substrate according to claim 1, wherein the patterning process is performed to form the alignment structures in the insulating layer in the abnormal alignment regions.

### Claim 3 (depends on 2)

The manufacturing method for a TFT array substrate according to claim 2, wherein the transparent conductive layer covers the insulating layer and the alignment structures, and a plurality of third alignment slits is formed along the alignment structures in the transparent conductive layer in each of the abnormal alignment regions.

### Claim 4 (depends on 3)

The manufacturing method for a TFT array substrate according to claim 3, wherein the first alignment slits are directly formed on the third alignment slits.

### Claim 5 (depends on 1)

The manufacturing method for a TFT array substrate according to claim 1, wherein the patterning process is performed to form the alignment structures in the transparent conductive layer in the abnormal alignment regions.

### Claim 6 (depends on 5)

The manufacturing method for a TFT array substrate according to claim 5, wherein the first alignment slits are directly formed on the alignment structures.

### Claim 7 (depends on 1)

The manufacturing method for a TFT array substrate according to claim 1, wherein the patterning process further includes using a half-tone photomask to form the alignment structures.

### Claim 8 (depends on 1)

The manufacturing method for a TFT array substrate according to claim 1, wherein a depth and a width of the first alignment slits are equal to a depth and a width of the second alignment slits.

### Claim 9 (depends on 8)

The manufacturing method for a TFT array substrate according to claim 8, wherein a depth and a width of the alignment structures are larger than the depth and the width of the first alignment slits.

### Claim 10 (depends on 1)

The manufacturing method for a TFT array substrate according to claim 1, wherein the normal alignment regions are respectively defined at a windward side of the scan lines corresponding to the alignment direction, at a windward side of the data lines corresponding to the alignment direction, at a windward side of the storage electrode lines corresponding to the alignment direction, and a windward side of the switch devices corresponding to the alignment direction.

### Claim 11 (depends on 1)

The manufacturing method for a TFT array substrate according to claim 1, wherein the abnormal alignment regions are respectively defined at a leeward side of the scan lines corresponding to the alignment direction, at a leeward side of the data lines corresponding to the alignment direction, at a leeward side of the storage electrode lines corresponding to the alignment direction, and at a leeward side of the switch devices corresponding to the alignment direction.