# US 8,541,281 B1 · Replacement gate process flow for highly scaled semiconductor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,541,281 B1 - Document ID: US8541281B1 - Status: Granted - Kind: B1 - Application number: 13/588,059 - Filed: 2012-08-17 - Granted: 2013-09-24 - Earliest claimed: 2012-08-17 - Assignees: Globalfoundries Inc. - Applicants: Stephan Kronholz; Ines Becker - Inventors: Stephan Kronholz; Ines Becker - Web page: https://patentgrep.com/patent/US8541281B1 ## CPC - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 84/0167: {Manufacturing their channels} - H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions} - H10D 84/0172: {Manufacturing their gate conductors} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A method disclosed herein includes forming sacrificial gate structures for a PFET and NFET transistor, removing the sacrificial gate structures and forming a replacement P-type gate structure for the PFET transistor and a replacement N-type gate structure for the NFET transistor, forming P-contact openings and N-contact openings in at least one layer of insulating material, wherein the P-contact openings expose portions of a P-active region and the N-contact openings expose portions of an N-active region, forming a masking layer that covers the exposed portions of the N-active region, performing an etching process though the P-contact openings in the layer of insulating material to define source/drain cavities in the P-active region proximate the replacement gate structure of the PFET transistor, and performing an epitaxial deposition process through the P-contact openings to form source/drain regions comprised of a semiconducting material in at least the source/drain cavities of the PFET transistor. ## Claims ### Claim 1 A method, comprising: forming sacrificial gate structures for both a PFET transistor and an NFET transistor above a semiconducting substrate, said sacrificial gate structures for said PFET transistor and said NFET transistor being formed above a P-active region and an N-active region, respectively, of said substrate; removing said sacrificial gate structures and forming a replacement P-type gate structure for said PFET transistor and a replacement N-type gate structure for said NFET transistor; after forming said replacement P-type and N-type gate structures, forming a plurality of P-contact openings and a plurality of N-contact openings in at least one layer of insulating material, wherein said P-contact openings expose portions of said P-active region and said N-contact openings expose portions of said N-active region; forming a masking layer that covers said exposed portions of said N-active region; with said masking layer in place, performing at least one etching process though said P-contact openings in said at least one layer of insulating material to define a plurality of source/drain cavities in said P-active region proximate said P-type replacement gate structure of said PFET transistor; and performing at least one epitaxial deposition process through said P-contact openings to form source/drain regions comprised of a semiconducting material in at least said source/drain cavities of said PFET transistor. ### Claim 2 (depends on 1) The method of claim 1, wherein said masking layer is comprised of silicon nitride or silicon oxynitride. ### Claim 3 (depends on 1) The method of claim 1, wherein performing at least one epitaxial deposition process to form source/drain regions comprised of a semiconducting material in said source/drain cavities of said PFET transistor comprises performing an in situ doping epitaxial deposition process to form raised P-doped silicon/germanium source/drain regions in said source/drain cavities of said PFET transistor. ### Claim 4 (depends on 1) The method of claim 1, wherein said replacement gate structures of said PFET transistor and said NFET transistor are comprised of the same materials. ### Claim 5 (depends on 1) The method of claim 1, wherein said replacement gate structures of said PFET transistor and said NFET transistor are comprised of different materials. ### Claim 6 (depends on 1) The method of claim 1, wherein said replacement gate structures of said PFET transistor and said NFET transistor are each comprised of a high-k gate insulation layer and at least one layer of metal formed above said high-k gate insulation layer. ### Claim 7 (depends on 1) The method of claim 1, wherein said masking layer covers said exposed portions of said N-active region while said epitaxial deposition process is performed. ### Claim 8 (depends on 1) The method of claim 1, further comprising, prior to removing said sacrificial gate structures of said NFET and PFET transistors, performing at least one ion implant process to form an implant region comprised of an N-type dopant material in said N-active region proximate said sacrificial gate structure of said NFET transistor. ### Claim 9 (depends on 8) The method of claim 8, further comprising, prior to removing said sacrificial gate structures of said NFET and PFET transistors, performing at least one ion implant process to form an implant region comprised of a P-type dopant material in said P-active region proximate said sacrificial gate structure of said PFET transistor. ### Claim 10 A method, comprising: forming sacrificial gate structures for both a PFET transistor and an NFET transistor above a P-active region and an N-active region, respectively, of a semiconducting substrate; forming at least one sidewall spacer proximate each of said sacrificial gate structures of each of said PFET and NFET transistors; forming a first layer of insulating material adjacent said sidewall spacer for each of said PFET and NFET transistors; removing said sacrificial gate structures of said PFET transistor and said NFET transistor to thereby define a gate cavity for each of said PFET transistor and said NFET transistor; forming a replacement P-type gate structure in said gate cavity of said PFET transistor and a replacement N-type gate structure in said gate cavity of said NFET transistor; after forming said replacement P-type and N-type gate structures for both of said PFET and NFET transistors, respectively, forming a second layer of insulating material above said first layer of insulating material; after forming said replacement P-type and N-type gate structures, forming a plurality of P-contact openings and a plurality of N-contact openings in said first and second layers of insulating material, wherein said P-contact openings expose portions of said P-active region and said N-contact openings expose portions of said N-active region; forming a masking layer that covers said exposed portions of said N-active region; with said masking layer in place, performing at least one etching process though said P-contact openings in said first and second layers of insulating material to define a plurality of source/drain cavities in said P-active region proximate said P-type replacement gate structure of said PFET transistor; and with said masking layer in place, performing at least one epitaxial deposition process through said P-contact openings to form source/drain regions comprised of a semiconducting material in at least said source/drain cavities of said PFET transistor. ### Claim 11 (depends on 10) The method of claim 10, wherein performing at least one epitaxial deposition process to form source/drain regions comprised of a semiconducting material in said source/drain cavities of said PFET transistor comprises performing an in situ doping epitaxial deposition process to form raised P-doped silicon/germanium source/drain regions in said source/drain cavities of said PFET transistor. ### Claim 12 (depends on 10) The method of claim 10, wherein said replacement gate structures of said PFET transistor and said NFET transistor are comprised of the same materials. ### Claim 13 (depends on 10) The method of claim 10, wherein said replacement gate structures of said PFET transistor and said NFET transistor are comprised of different materials. ### Claim 14 (depends on 10) The method of claim 10, wherein said replacement gate structures of said PFET transistor and said NFET transistor are each comprised of a high-k gate insulation layer and at least one layer of metal formed above said high-k gate insulation layer. ### Claim 15 (depends on 10) The method of claim 10, wherein said masking layer covers said exposed portions of said N-active region while said epitaxial deposition process is performed. ### Claim 16 (depends on 10) The method of claim 10, wherein said masking layer is comprised of silicon nitride or silicon oxynitride. ### Claim 17 (depends on 10) The method of claim 10, further comprising, prior to removing said sacrificial gate structures of said NFET and PFET transistors, performing at least one ion implant process to form an implant region comprised of an N-type dopant material in said N-active region proximate said sacrificial gate structure of said NFET transistor. ### Claim 18 (depends on 17) The method of claim 17, further comprising, prior to removing said sacrificial gate structures of said NFET and PFET transistors, performing at least one ion implant process to form an implant region comprised of a P-type dopant material in said P-active region proximate said sacrificial gate structure of said PFET transistor.