# US 8,541,280 B2 · Semiconductor structure and method for manufacturing the same

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- Number: US 8,541,280 B2
- Document ID: US8541280B2
- Status: Granted
- Kind: B2
- Application number: 13/380,654
- Filed: 2011-04-18
- Published: 2013-01-03
- Granted: 2013-09-24
- Earliest claimed: 2010-09-29
- Assignees: Institute of Microelectronics, Chinese Academy of Sciences
- Applicants: Haizhou Yin; Zhijiong Luo; Huilong Zhu
- Inventors: Haizhou Yin; Zhijiong Luo; Huilong Zhu
- Web page: https://patentgrep.com/patent/US8541280B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: depositing an interlayer dielectric layer (105) on a semiconductor substrate (101) to cover a source/drain region (102) and a gate stack on the semiconductor substrate (101); etching the interlayer dielectric layer and the source/drain region, so as to form a contact hole (110) extending into the source/drain region; conformally forming an amorphous layer (111) on an exposed part of the source/drain region; forming a metal silicide layer (113) on a surface of the amorphous layer (111); and filling the contact hole (110) with a contact metal (114). Correspondingly, the present invention further provides a semiconductor structure. The present invention etches the source/drain region so that the exposed part comprises the bottom and a sidewall, thereby expanding the contact area between the contact metal in the contact hole and the source/drain region, and reducing the contact resistance. The present invention effectively eliminates EOR defects caused by the amorphous ion implantation by forming an amorphous substance by a selective deposition.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
depositing an interlayer dielectric layer (105) on a semiconductor substrate (101) to cover a source/drain region (102) and a gate stack on the semiconductor substrate (101);
etching the interlayer dielectric layer (105) and the source/drain region (102), so as to expose a part of the source/drain region (102) and form a contact hole (110) extending into the source/drain region (102);
conformally forming an amorphous layer (111) on the exposed part of the source/drain region (102);
forming a metal silicide layer (113) on a surface of the amorphous layer (111); and
filling the contact hole (110) with a contact metal (114).

### Claim 2 (depends on 1)

The method according to claim 1, wherein
the amorphous layer (111) is conformally formed by a selective deposition process or an epitaxial growth process.

### Claim 3 (depends on 1)

The method according to claim 1, wherein
the amorphous layer (111) has a thickness larger than a portion thereof used for forming the metal silicide layer.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the amorphous layer is one of amorphous silicon, amorphous SiGe and amorphous SiC.

### Claim 5 (depends on 1)

The method according to claim 1, wherein after conformally forming the amorphous layer (111), the method further comprises implanting doping ions into the amorphous layer (111).

### Claim 6 (depends on 1)

The method according to claim 1, wherein the exposed part of the source/drain region (102) comprises the bottom of the contact hole (110) and a part of the sidewall extending from the bottom.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the source/drain region (102) is a raised source/drain region.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the contact metal (114) is made of one of W, TiAl alloy and Al, or combinations thereof.

### Claim 9 (depends on 1)

The method according to claim 1, wherein
the source/drain region (102) comprises an etching stop layer made of a material different from that of other portions in the source/drain region.

### Claim 10 (depends on 9)

The method according to claim 9, wherein
the etching stop layer is flushed with the bottom of the gate stack.

### Claim 11 (depends on 9)

The method according to claim 9, wherein
the etching stop layer is made of silicon; and
a portion in the source/drain region above the etching stop layer is made of SiGe.