# US 8,541,278 B2 · Method for fabricating super-junction power device with reduced miller capacitance

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- Number: US 8,541,278 B2
- Document ID: US8541278B2
- Status: Granted
- Kind: B2
- Application number: 13/234,132
- Filed: 2011-09-15
- Published: 2012-11-22
- Granted: 2013-09-24
- Earliest claimed: 2011-05-19
- Assignees: Anpec Electronics Corporation
- Applicants: Yung-Fa Lin; Shou-Yi Hsu; Meng-Wei Wu; Main-Gwo Chen; Yi-Chun Shih
- Inventors: Yung-Fa Lin; Shou-Yi Hsu; Meng-Wei Wu; Main-Gwo Chen; Yi-Chun Shih
- Web page: https://patentgrep.com/patent/US8541278B2

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/159: {Shapes}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 32/141: {the applied layer comprising oxides only}
- H10P 32/1412: {through the applied layer}
- H10P 32/171: {being group IV material}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.

## Claims

### Claim 1

A method for fabricating a super-junction power device with reduced miller capacitance, comprising:
providing an N-type substrate serving as a drain of the super-junction power device;
forming a P-type epitaxial layer on the N-type substrate;
forming at least a trench in the P-type epitaxial layer within a cell region;
forming a buffer layer on an interior surface in the trench;
filling an N-type dopant layer into the trench;
etching the N-type dopant layer to form a recessed structure at an upper portion of the trench;
forming a gate oxide layer in the recessed structure, and simultaneously making dopants in the n-type dopant layer diffuse into the P-type epitaxial layer through the buffer layer to form an N-type diffusion layer;
filling a gate conductor into the recessed structure; and
forming an N-type source doped region around the gate conductor in the P-type epitaxial layer.

### Claim 2 (depends on 1)

The method for fabricating a super-junction power device with reduced Miller capacitance according to claim 1, wherein the gate conductor, the gate oxide layer, the N-type source doped region and the N-type diffusion layer constitute a vertical transistor.

### Claim 3 (depends on 2)

The method for fabricating a super-junction power device with reduced Miller capacitance according to claim 2, wherein the vertical transistor has a vertical channel between the N-type source doped region and the N-type diffusion layer.

### Claim 4 (depends on 1)

The method for fabricating a super-junction power device with reduced Miller capacitance according to claim 1, wherein the trench reaches the N-type substrate.

### Claim 5 (depends on 1)

The method for fabricating a super-junction power device with reduced Miller capacitance according to claim 1, wherein the buffer layer is formed by thermal oxidation.

### Claim 6 (depends on 1)

The method for fabricating a super-junction power device with reduced Miller capacitance according to claim 1, wherein the buffer layer comprises silicon oxide.

### Claim 7 (depends on 1)

The method for fabricating a super-junction power device with reduced Miller capacitance according to claim 1, wherein the N-type dopant layer comprises arsenic-doped silicate glass.

### Claim 8 (depends on 1)

The method for fabricating a super-junction power device with reduced Miller capacitance according to claim 1, further comprising:
forming a P-type well in the P-type epitaxial layer.

### Claim 9 (depends on 8)

The method for fabricating a super-junction power device with reduced Miller capacitance according to claim 8, wherein the P-type well has a doping concentration that is greater than that of the P-type epitaxial layer.

### Claim 10 (depends on 8)

The method for fabricating a super-junction power device with reduced Miller capacitance according to claim 8, wherein a depth of the recessed structure is substantially equal to a junction depth of the P-type well.

### Claim 11 (depends on 1)

The method for fabricating a super-junction power device with reduced Miller capacitance according to claim 1, wherein the gate conductor comprises polysilicon.

### Claim 12 (depends on 1)

The method for fabricating a super-junction power device with reduced Miller capacitance according to claim 1, wherein the gate conductor is in direct contact with the N-type dopant layer.