# US 8,541,275 B2 · Single metal gate CMOS integration by intermixing polarity specific capping layers

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- Number: US 8,541,275 B2
- Document ID: US8541275B2
- Status: Granted
- Kind: B2
- Application number: 12/616,941
- Filed: 2009-11-12
- Published: 2011-05-12
- Granted: 2013-09-24
- Earliest claimed: 2009-11-12
- Assignees: International Business Machines Corporation
- Applicants: Sivananda Kanakasabapathy; Hemanth Jagannathan; Matthew Copel
- Inventors: Sivananda Kanakasabapathy; Hemanth Jagannathan; Matthew Copel
- Web page: https://patentgrep.com/patent/US8541275B2

## CPC

- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for forming a complementary metal oxide semiconductor device includes forming a first capping layer on a dielectric layer, blocking portions in the capping layer in regions where the capping layer is to be preserved using a block mask. Exposed portions of the first capping layer are intermixed with the dielectric layer to form a first intermixed layer. The block mask is removed. The first capping layer and the first intermixed layer are etched such that the first capping layer is removed to re-expose the dielectric layer in regions without removing the first intermixed layer.

## Claims

### Claim 1

A method for forming a complementary metal oxide semiconductor device, comprising:
forming a first capping layer on a dielectric layer;
blocking portions of the capping layer in regions where the capping layer is to be preserved using a block mask;
at exposed portions of the first capping layer, performing an inert bombardment of noble gas ions from a plasma discharge to intermix elements of the first capping layer into the dielectric layer to form a first intermixed layer;
removing the block mask; and
etching the first capping layer such that the first capping layer is removed to re-expose the dielectric layer in regions without removing the first intermixed layer.

### Claim 2 (depends on 1)

The method as recited in claim 1, wherein forming a first capping layer includes forming at least one of lanthanum oxide and aluminum oxide.

### Claim 3 (depends on 1)

The method as recited in claim 1, wherein etching the first capping layer and the first intermixed layer includes performing a maskless wet etching wherein the first capping layer is selectively removed while the first intermixed layer remains intact.

### Claim 4 (depends on 1)

The method as recited in claim 1, further comprising:
forming a second capping layer on the re-exposed dielectric layer and the first intermixed layer;
blocking portions in the second capping layer in regions where the second capping layer is to be preserved using a second block mask;
intermixing elements of the second capping layer into the dielectric layer to form a second intermixed layer;
removing the second block mask; and
etching the second capping layer such that the second capping layer is removed to re-expose the first intermixed layer in regions without removing the second intermixed layer.

### Claim 5 (depends on 4)

The method as recited in claim 4, wherein the first capping layer includes a material compatible with a first type field effect transistor (FET) structure and the second capping layer includes a material compatible with a second type FET structure.

### Claim 6 (depends on 1)

The method as recited in claim 1, further comprising:
forming transistors using the first intermixed layer for a first transistor type and using the second intermixed layer for a second transistor type such that a single metal, single dielectric type device is fabricated.

### Claim 7 (depends on 6)

The method as recited in claim 6, wherein forming transistors includes forming n-type field effect transistors (FETs) using the first intermixed layer and p-type FETs using the second intermixed layer.

### Claim 8 (depends on 6)

The method as recited in claim 6, wherein forming transistors includes forming FETs having different threshold voltages using at least the first intermixed layer and the second intermixed layer.

### Claim 9

A method for forming a complementary metal oxide semiconductor device, comprising:
forming a first capping layer on a dielectric layer;
blocking portions in the capping layer in regions where the capping layer is to be preserved using a block mask;
bombarding exposed portions of the first capping layer with noble gas ions from a plasma discharge to drive elements of the first capping layer into the dielectric layer to form a first intermixed layer;
removing the block mask;
etching the first capping layer such that the first capping layer is removed to re-expose the dielectric layer in regions without removing the first intermixed layer;
forming a second capping layer on the re-exposed dielectric layer and the first intermixed layer;
blocking portions in the second capping layer in regions where the second capping layer is to be preserved using a second block mask;
bombarding exposed portions of the second capping layer with noble gas ions from a plasma discharge to drive elements of the second capping layer into the dielectric layer to form a second intermixed layer;
removing the second block mask;
etching the second capping layer and the second intermixed layer such that the second capping layer is removed to re-expose the first intermixed layer in regions without removing the second intermixed layer; and
forming transistors using the first intermixed layer for a first transistor type and using the second intermixed layer for a second transistor type.

### Claim 10 (depends on 9)

The method as recited in claim 9, wherein forming a first capping layer includes forming at least one of lanthanum oxide and aluminum oxide.

### Claim 11 (depends on 9)

The method as recited in claim 9, wherein etching the first capping layer and the first intermixed layer includes performing a maskless wet etching wherein the first capping layer is selectively removed while the first intermixed layer remains intact.

### Claim 12 (depends on 9)

The method as recited in claim 9, wherein forming transistors includes forming n-type field effect transistors (FETs) using the first intermixed layer and p-type FETs using the second intermixed layer.

### Claim 13 (depends on 9)

The method as recited in claim 9, wherein forming transistors includes forming FETs having different threshold voltages using at least the first intermixed layer and the second intermixed layer.

### Claim 14 (depends on 9)

The method as recited in claim 9, wherein forming transistors includes forming gate structures for a complementary metal oxide semiconductor (CMOS) device including the first intermixed layer for an nFET device and the second intermixed layer in a pFET device.