# US 8,541,274 B1 · Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed after source/drain formation

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- Number: US 8,541,274 B1
- Document ID: US8541274B1
- Status: Granted
- Kind: B1
- Application number: 13/609,828
- Filed: 2012-09-11
- Granted: 2013-09-24
- Earliest claimed: 2012-09-11
- Assignees: Globalfoundries Inc.
- Applicants: Ruilong Xie; Xiuyu Cai, Jr.; Kangguo Cheng; Ali Khakifirooz
- Inventors: Ruilong Xie; Xiuyu Cai, Jr.; Kangguo Cheng; Ali Khakifirooz
- Web page: https://patentgrep.com/patent/US8541274B1

## CPC

- H10D 86/011: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a sacrificial gate structure above the fin, forming sidewall spacers adjacent at least a portion of the sacrificial gate structure and removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin. The method also includes the steps of performing a fin reflow process on the exposed portions of the fin to define a nanowire structure having a cross-sectional configuration that is different from the first cross-sectional configuration and forming a replacement gate structure in the gate cavity and at least partially around the nanowire structure.

## Claims

### Claim 1

A method of forming a FinFET device, comprising:
forming a fin comprised of a semiconducting material, said fin having a first, as-formed cross-sectional configuration;
forming a sacrificial gate structure above said fin;
forming sidewall spacers adjacent at least a portion of said sacrificial gate structure;
removing said sacrificial gate structure to thereby define a gate cavity that exposes a portion of said fin, wherein said gate cavity is laterally defined by said spacers;
performing a fin reflow process on said exposed portions of said fin to define a nanowire structure having a cross-sectional configuration that is different from said first cross-sectional configuration; and
forming a replacement gate structure in said gate cavity and at least partially around said nanowire structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein said first cross-sectional configuration of said fin is approximately rectangular and wherein said cross-sectional configuration of said nanowire structure is approximately circular or approximately elliptical.

### Claim 3 (depends on 1)

The method of claim 1, wherein an as-formed cross-sectional area of said fin is approximately equal to a cross-sectional area of said nanowire structure.

### Claim 4 (depends on 1)

The method of claim 1, wherein said semiconducting material is comprised of silicon.

### Claim 5 (depends on 1)

The method of claim 1, wherein performing said fin reflow process comprises performing a hydrogen anneal process.

### Claim 6 (depends on 5)

The method of claim 5, wherein said hydrogen anneal process is performed within the range of about 900-1100° C. for a duration of about 60-600 seconds.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming said replacement gate structure in said gate cavity comprises forming said replacement gate structure in said gate cavity and completely around an outer surface of said nanowire structure.

### Claim 8 (depends on 1)

The method of claim 1, wherein said sacrificial gate structure is comprised of a silicon dioxide gate insulation layer and a polysilicon gate electrode positioned above said gate insulation layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein said replacement gate structure comprises a gate insulation layer comprised of a high-k insulating material and a gate electrode comprised of at least one layer of metal.

### Claim 10

A method of forming a FinFET device, comprising:
forming a fin comprised of silicon, said fin having a first, as-formed cross-sectional configuration;
forming a sacrificial gate structure above said fin;
forming sidewall spacers adjacent at least a portion of said sacrificial gate structure;
removing said sacrificial gate structure to thereby define a gate cavity that exposes a portion of said fin, wherein said gate cavity is laterally defined by said spacers;
performing a hydrogen anneal process on said exposed portions of said fin to define a nanowire structure having a cross-sectional configuration that is different from said first cross-sectional configuration; and
forming a replacement gate structure in said gate cavity and completely around an outer surface of said nanowire structure.

### Claim 11 (depends on 10)

The method of claim 10, wherein said first cross-sectional configuration of said fin is approximately rectangular and wherein said cross-sectional configuration of said nanowire structure is approximately circular or approximately elliptical.

### Claim 12 (depends on 10)

The method of claim 10, wherein an as-formed cross-sectional area of said fin is approximately equal to a cross-sectional area of said nanowire structure.

### Claim 13 (depends on 10)

The method of claim 10, wherein said hydrogen anneal process is performed within the range of about 900-1100° C. for a duration of about 60-600 seconds.

### Claim 14 (depends on 10)

The method of claim 10, wherein said sacrificial gate structure is comprised of a silicon dioxide gate insulation layer and a polysilicon gate electrode positioned above said gate insulation layer.

### Claim 15 (depends on 10)

The method of claim 10, wherein said replacement gate structure comprises a gate insulation layer comprised of a high-k insulating material and a gate electrode comprised of at least one layer of metal.