# US 8,541,272 B2 · Method of manufacturing semiconductor device with offset sidewall structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,541,272 B2 - Document ID: US8541272B2 - Status: Granted - Kind: B2 - Application number: 13/833,891 - Filed: 2013-03-15 - Published: 2013-08-08 - Granted: 2013-09-24 - Earliest claimed: 2001-09-21 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Kazunobu Ota; Hirokazu Sayama; Hidekazu Oda - Web page: https://patentgrep.com/patent/US8541272B2 ## CPC - H10D 64/516: {the thicknesses being non-uniform} - H10D 64/01302: {the insulator being formed after the semiconductor body, the semiconductor being silicon} - H10D 64/01332: {Making the insulator} - H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)} - H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials} - H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions} - H10D 84/0181: {Manufacturing their gate insulating layers} - H10D 84/0184: {Manufacturing their gate sidewall spacers} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10P 14/69215: {the material being a silicon oxide, e.g. SiO2} - H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz} - H10P 30/20: into semiconductor materials, e.g. for doping - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62). ## Claims ### Claim 1 A method of manufacturing a semiconductor device including a first n-type MISFET formed in a first region of a semiconductor substrate, a first p-type MISFET formed in a second region of the semiconductor substrate, a second n-type MISFET formed in a third region of the semiconductor substrate and having a thicker gate insulating film than the first n-type MISFET, and a second p-type MISFET formed in a fourth region of the semiconductor substrate and having a thicker gate insulating film than the first p-type MISFET, comprising steps of: (a) forming a gate insulating film of the first n-type MISFET over the first region, and forming a gate insulating film of the first p-type MISFET over the second region; (b) forming a first gate electrode over the gate insulating film of the first n-type MISFET, and forming a second gate electrode over the gate insulating film of the first p-type MISFET; (c) after the step (b), forming first insulating films over side surfaces of the first gate electrode and over side surfaces of the second gate electrode; (d) after the step (c), etching the first insulating films such that the first insulating films are kept on side surfaces of the first and second gate electrodes, and such that surfaces of the first and second regions are exposed; (e) after the step (d), forming epitaxial layers on the exposed surfaces of the first and second regions; (f) after the step (e), under a condition which a first resist pattern covers the second region, forming first n-type impurity regions in the first region by ion implantation method; (g) after the step (f), forming second insulating films over the side surfaces of the first gate electrode via the first insulating films and over the side surfaces of the second gate electrode via the first insulating films; (h) after the step (g), under a condition which a second resist pattern covers the first region, forming first p-type impurity regions in the second region by ion implantation method; (i) after the step (g), forming third insulating films over the side surfaces of the first gate electrode via the first and second insulating films, and over the side surfaces of the second gate electrode via the first and second insulating films, wherein a thickness of each the third insulating film is thicker than a thickness of each the first insulating film and each the second insulating film; (j) after the step (i), under a condition which a third resist pattern covers the second region, forming second n-type impurity regions in the first region by ion implantation method, wherein an impurity concentration of each the second n-type impurity region is higher than an impurity concentration of each the first n-type impurity region; and (k) after the step (i), under a condition which a fourth resist pattern covers the first region, forming second p-type impurity regions in the second region by ion implantation method, wherein an impurity concentration of each the second p-type impurity region is higher than an impurity concentration of each the first p-type impurity region. ### Claim 2 (depends on 1) A method of manufacturing a semiconductor device according to the claim 1, further comprising a step of forming a p-type pocket region in the first region during the step (f). ### Claim 3 (depends on 1) A method of manufacturing a semiconductor device according to the claim 1, further comprising a step of forming an n-type pocket region in the second region during the step (h). ### Claim 4 (depends on 1) A method of manufacturing a semiconductor device according to the claim 1, further comprising steps of: (1) before the step (c), forming a gate insulating film of the second n-type MISFET over the third region, and forming a gate insulating film of the second p-type MISFET over the fourth region; (m) after the step (1) and before the step (c), forming a third gate electrode over the gate insulating film of the second n-type MISFET, and forming a fourth gate electrode over the gate insulating film of the second p-type MISFET; (n) after the step (m) and before the step (c), forming third n-type impurity regions in the third region; and (o) after the step (m) and before the step (c), forming third p-type impurity regions in the fourth region. ### Claim 5 (depends on 4) A method of manufacturing a semiconductor device according to the claim 4, wherein, in the step (j), fourth n-type impurity regions having higher impurity concentration than the third n-type impurity regions are formed in the third region, and wherein, in the step (k), fourth p-type impurity regions having higher impurity concentration than the third p-type impurity regions are formed in the fourth region. ### Claim 6 (depends on 1) A method of manufacturing a semiconductor device according to the claim 1, wherein each the first insulating film includes a silicon oxide film. ### Claim 7 (depends on 1) A method of manufacturing a semiconductor device according to the claim 1, wherein each the second insulating film includes a silicon oxide film. ### Claim 8 (depends on 1) A method of manufacturing a semiconductor device according to the claim 1, wherein each the third insulating film includes a silicon nitride film. ### Claim 9 (depends on 1) A method of manufacturing a semiconductor device according to the claim 1, wherein each the third insulating film is a spacer state.