# US 8,541,262 B2 · Die edge contacts for semiconductor devices

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- Number: US 8,541,262 B2
- Document ID: US8541262B2
- Status: Granted
- Kind: B2
- Application number: 12/874,816
- Filed: 2010-09-02
- Published: 2012-03-08
- Granted: 2013-09-24
- Earliest claimed: 2010-09-02
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Yi-Jen Lai; You-Hua Chou; Hon-Lin Huang; Huai-Tei Yang
- Inventors: Yi-Jen Lai; You-Hua Chou; Hon-Lin Huang; Huai-Tei Yang
- Web page: https://patentgrep.com/patent/US8541262B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 90/00: Package configurations
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/019: {of bond pads}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/834: {Interconnections on sidewalls of chips}
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.

## Claims

### Claim 1

A method of forming a semiconductor structure, the method comprising:
providing a wafer having one or more contacts formed thereon;
forming a passivation layer over the wafer, the passivation layer being patterned to expose the one or more contacts and to form trenches extending from respective ones of the contacts to a scribe line;
forming a conductive material in the trenches; and
separating the wafer into a plurality of dies along the scribe line, wherein at least a portion of the conductive material in the trenches are exposed along an edge of a die.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming through-substrate vias in the wafer below the trenches along the scribe line, the conductive material in the trenches being electrically coupled to respective ones of the through-substrate vias.

### Claim 3 (depends on 1)

The method of claim 1, further comprising forming a groove through the conductive material in the trench prior to the separating.

### Claim 4 (depends on 3)

The method of claim 3, wherein the forming a groove is performed at least in part by lasing.

### Claim 5 (depends on 1)

The method of claim 1, wherein the passivation layer has a thickness between about 1,000 Å and about 30,000 Å.

### Claim 6 (depends on 1)

The method of claim 1, wherein the trench at the scribe line has a thickness of about 800 Å and about 30,000 Å.

### Claim 7

A method of forming a semiconductor structure, the method comprising:
providing one or more integrated circuit dies, each of the integrated circuit dies having die edge contacts, the die edge contacts comprising a first conductive layer in a passivation layer and a second conductive layer on the first conductive layer, the second conductive layer extending above the passivation layer;
providing an inner connection structure, the inner connection structure comprising one or more inner connection substrates, at least one of the inner connection substrates having electrical contacts formed thereon; and
placing the one or more integrated circuit dies into the inner connection structure such that the die edge contacts of the one or more integrated circuit dies are electrically coupled to respective ones of the electrical contacts of the at least one of inner connection substrates, wherein the inner connection substrates are perpendicular to a major surface of the integrated circuit dies.

### Claim 8 (depends on 7)

The method of claim 7, wherein the inner connection structure further comprises external contacts along an edge of at least one of the inner connection substrates.

### Claim 9 (depends on 7)

The method of claim 7, wherein the inner connection structure further comprises one or more die supports protruding from the inner connection substrates.

### Claim 10 (depends on 7)

The method of claim 7, further comprising an outer shell on a side of the inner connection structure opposite the integrated circuit dies.

### Claim 11 (depends on 10)

The method of claim 10, further comprising one or more micro-suspension rods interposed between the outer shell and the inner connection structure.

### Claim 12 (depends on 7)

The method of claim 7, wherein the die edge contacts comprise a through-substrate via.

### Claim 13 (depends on 7)

The method of claim 7, wherein the die edge contacts comprise an exposed portion of a trench in the integrated circuit dies.

### Claim 14

A method of forming a semiconductor structure, the method comprising:
providing one or more integrated circuit dies, each of the integrated circuit dies having die edge contacts;
providing an inner connection structure, the inner connection structure comprising one or more inner connection substrates, at least one of the inner connection substrates having electrical contacts formed thereon, the inner connection structure having an outer shell on a side of the inner connection structure opposite the integrated circuit dies, the outer shell being different than a surface of the inner connection structure; and
placing the one or more integrated circuit dies into the inner connection structure such that the die edge contacts of the one or more integrated circuit dies are electrically coupled to respective ones of the electrical contacts of the at least one of inner connection substrates, wherein the inner connection substrates are perpendicular to a major surface of the integrated circuit dies.

### Claim 15 (depends on 14)

The method of claim 14, wherein the inner connection structure further comprises external contacts along an edge of at least one of the inner connection substrates.

### Claim 16 (depends on 14)

The method of claim 14, wherein the inner connection structure further comprises one or more die supports protruding from the inner connection substrates.

### Claim 17 (depends on 14)

The method of claim 14, further comprising one or more micro-suspension rods interposed between the outer shell and the inner connection structure.

### Claim 18 (depends on 14)

The method of claim 14, wherein the die edge contacts comprise a through-substrate via.

### Claim 19 (depends on 14)

The method of claim 14, wherein the die edge contacts comprise an exposed portion of a trench in the integrated circuit dies.