# US 8,541,261 B2 · Method for manufacturing a package-on-package type semiconductor device

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- Number: US 8,541,261 B2
- Document ID: US8541261B2
- Status: Granted
- Kind: B2
- Application number: 13/666,125
- Filed: 2012-11-01
- Published: 2013-03-07
- Granted: 2013-09-24
- Earliest claimed: 2009-10-15
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Takashi Kikuchi; Tomoaki Hashimoto; Tatsuya Hirai
- Web page: https://patentgrep.com/patent/US8541261B2

## CPC

- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/016: {using moulds}
- H10W 90/00: Package configurations
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07521: {Aligning}
- H10W 72/30: Die-attach connectors
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/20: Configurations of stacked chips
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Bump electrodes (conductive members) bonded onto lands disposed at a peripheral portion side than terminals (bonding leads) electrically coupled to pads (electrode pads) of a microcomputer chip (semiconductor chip) are sealed with sealing resin (a sealing body). Thereafter, the sealing resin is ground (removed) partially such that a part of each of the bump electrodes is exposed. The step of protruding the part of each of the bump electrodes from a front surface of the sealing resin is performed, after the grinding step.

## Claims

### Claim 1

A method of manufacturing a semiconductor device comprising the steps of:
(a) providing a first wiring substrate including a first upper surface, a plurality of first bonding leads formed on the first upper surface, a plurality of first lands formed on the first upper surface and arranged closer to a peripheral portion of the first upper surface than the first bonding leads, a first lower surface opposite the first upper surface, and a plurality of second lands formed on the first lower surface, the first lands being electrically connected with the first bonding leads, respectively;
(b) disposing a plurality of electrodes over the first lands of the first wiring substrate, respectively, and mounting a first semiconductor chip over the first upper surface of the first wiring substrate, each of the electrodes being comprised of a solder material, the first semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a back surface opposite the main surface;
(c) electrically connecting the pads of the first semiconductor chip with the first bonding leads of the first wiring substrate via a plurality of conductive members, respectively;
(d) sealing the first semiconductor chip and the electrodes with resin forming a sealing body;
(e) after the step (d), removing a portion of the sealing body such that a part of each of the electrodes is exposed from an upper surface of the sealing body;
(f) after the step (e), performing a heat treatment without stacking another member on the electrodes such that the part of each of the electrodes is caused to protrude from the upper surface of the sealing body; and
(g) after the step (f), stacking a second wiring substrate over the upper surface of the sealing body and electrically connecting a plurality of third lands of the second wiring substrate with the first lands of the first wiring substrate via the electrodes, respectively,
wherein the second wiring substrate includes a second main surface, a plurality of fourth lands formed on the second main surface, a second back surface opposite the second main surface, and the third lands formed on the second back surface, and
the third lands are electrically connected with the fourth lands, respectively.

### Claim 2 (depends on 1)

The method according to claim 1, wherein step (e) includes grinding the upper surface of the sealing body.

### Claim 3 (depends on 1)

The method according to claim 1, wherein step (f) includes cooling the electrodes such that a portion of each of the electrodes is caused to separate from the sealing body.

### Claim 4 (depends on 1)

The method according to claim 1, wherein, when performing the heat treatment in step (f), a plurality of solder balls are bonded to surfaces of the second lands, respectively.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising:
(h) after step (g), mounting a second semiconductor device over the second upper surface of the second wiring substrate and electrically connecting a plurality of fifth lands of the second semiconductor device with the fourth lands of the second wiring substrate, respectively,
wherein the second semiconductor device has a third wiring substrate and a second semiconductor chip,
the third wiring substrate includes a third upper surface, a plurality of terminals formed on the third upper surface, a third lower surface opposite the third upper surface, and the fifth lands formed on the third lower surface, and
the fifth lands are electrically connected with the terminals, respectively.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the first semiconductor chip is mounted over the first upper surface of the first wiring substrate via an adhesive material comprised of a film type, and
wherein the adhesive material is cured in step (d).