# US 8,541,258 B2 · Thin film transistor, method of manufacturing the same and flat panel display device having the same

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- Number: US 8,541,258 B2
- Document ID: US8541258B2
- Status: Granted
- Kind: B2
- Application number: 13/091,614
- Filed: 2011-04-21
- Published: 2011-08-11
- Granted: 2013-09-24
- Earliest claimed: 2008-06-30
- Assignees: Samsung Display Co., Ltd.
- Applicants: Min-Kyu Kim; Jong-Han Jeong; Tae-Kyung Ahn; Jae-Kyeong Jeong; Yeon-Gon Mo; Jin-Seong Park; Hyun-Joong Chung; Kwang-Suk Kim; Hui-Won Yang
- Inventors: Min-Kyu Kim; Jong-Han Jeong; Tae-Kyung Ahn; Jae-Kyeong Jeong; Yeon-Gon Mo; Jin-Seong Park; Hyun-Joong Chung; Kwang-Suk Kim; Hui-Won Yang
- Web page: https://patentgrep.com/patent/US8541258B2

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6704: {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A thin film transistor (TFT) using an oxide semiconductor as an active layer, a method of manufacturing the TFT, and a flat panel display device having the TFT include source and drain electrodes formed on a substrate; an active layer formed of an oxide semiconductor disposed on the source and drain electrodes; a gate electrode; and an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer. In the TFT, the interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV. Since the interfacial stability layer has the same characteristics as a gate insulating layer and a passivation layer, chemically high interface stability is maintained. Since the interfacial stability layer has a band gap equal to or greater than that of the active layer, charge trapping is physically prevented.

## Claims

### Claim 1

A method of manufacturing a thin film transistor, comprising:
forming source and drain electrodes on a substrate;
sequentially forming a first interfacial stability layer and an oxide semiconductor layer on the substrate having the source and drain electrodes;
patterning the oxide semiconductor layer to form an active layer;
forming a gate insulating layer on the substrate to cover the active layer; and
forming a gate electrode on the gate insulating layer above the active layer, wherein the first interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV, and a portion of the interfacial stability layer is disposed between the source and drain electrodes and the active layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first interfacial stability layer comprises one selected from the group consisting of SiOx, SiOxNy, SiOxCy, SiOxCyHz, SiOxFy, GeOx, GdOx, AlOx, GaOx, SbO, ZrOx, HfOx, TaOx, YOx, VOx, MgOx, CaOx, BaOx, SrOx, and SOG.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first interfacial stability layer is formed using a physical deposition method.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first interfacial stability layer is formed to a thickness of 10 to 20 Å.

### Claim 5 (depends on 1)

The method of claim 1, wherein the oxide semiconductor layer comprises zinc oxide (ZnO).

### Claim 6 (depends on 5)

The method of claim 5, wherein the oxide semiconductor layer is doped with at least one ion of gallium (Ga), indium (In), tin (Sn), zirconium (Zr), hafnium (Hf), cadmium (Cd), silver (Ag), copper (Cu), germanium (Ge), gadolinium (Gd), and vanadium (V).

### Claim 7 (depends on 1)

The method of claim 1, wherein the first interfacial stability layer is patterned in the forming the active layer.

### Claim 8 (depends on 1)

The method of claim 1, further comprising forming a second interfacial stability layer on the active layer opposite the first interfacial stability layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the second interfacial stability layer comprises one selected from the group consisting of SiOx, SiOxNy, SiOxCy, SiOxCyHz, SiOxFy, GeOx, GdOx, AlOx, GaOx, SbO, ZrOx, HfOx, TaOx, YOx, VOx, MgOx, CaOx, BaOx, SrOx and SOG.

### Claim 10 (depends on 9)

The method of claim 9, wherein the second interfacial stability layer is formed using a physical deposition method.

### Claim 11 (depends on 8)

The method of claim 8, wherein the second interfacial stability layer is formed to a thickness of 50 to 5000 Å.

### Claim 12

A method of manufacturing a thin film transistor, comprising:
forming source and drain electrodes on a substrate;
sequentially forming an oxide semiconductor layer and an interfacial stability layer on the substrate having the source and drain electrodes;
patterning the interfacial stability layer and the oxide semiconductor layer to form an active layer;
forming a gate insulating layer on the substrate having the active layer; and
forming a gate electrode on the gate insulating layer above the active layer,
wherein the interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV, and a portion of the interfacial stability layer is disposed between the source and drain electrodes and the active layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the oxide semiconductor layer comprises zinc oxide (ZnO).

### Claim 14 (depends on 13)

The method of claim 13, wherein the oxide semiconductor layer is doped with at least one ion of gallium (Ga), indium (In), tin (Sn), zirconium (Zr), hafnium (Hf), cadmium (Cd), silver (Ag), copper (Cu), germanium (Ge), gadolinium (Gd), and vanadium (V).

### Claim 15 (depends on 12)

The method of claim 12, wherein the interfacial stability layer comprises one selected from the group consisting of SiOx, SiOxNy, SiOxCy, SiOxCyHz, SiOxFy, GeOx, GdOx, AlOx, GaOx, SbO, ZrOx, HfOx, TaOx, YOx, VOx, MgOx, CaOx, BaOx, SrOx, and SOG.

### Claim 16 (depends on 12)

The method of claim 12, wherein the interfacial stability layer is formed using a physical deposition method.

### Claim 17 (depends on 12)

The method of claim 12, wherein the interfacial stability layer is formed to a thickness of 50 to 5000 Å.