# US 8,541,255 B2 · Solid-state imaging device, method of manufacturing the same, and imaging apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,541,255 B2 - Document ID: US8541255B2 - Status: Granted - Kind: B2 - Application number: 12/656,695 - Filed: 2010-02-12 - Published: 2010-06-17 - Granted: 2013-09-24 - Earliest claimed: 2007-05-29 - Assignees: Sony Corporation - Applicants: Keiji Mabuchi - Inventors: Keiji Mabuchi - Web page: https://patentgrep.com/patent/US8541255B2 ## CPC - H10F 39/151: {Geometry or disposition of pixel elements, address lines or gate electrodes} - H10F 39/014: {of CMOS image sensors} - H10F 39/12: Image sensors - H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors - H10F 39/803: {Pixels having integrated switching, control, storage or amplification elements} - H10F 39/807: {Pixel isolation structures} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract A solid-state imaging device includes a semiconductor substrate; a first conductive region of the semiconductor substrate; a first conductive region on an upper surface side of the first conductive region of the semiconductor substrate; a second conductive region below the first conductive region on the upper surface side of the first conductive region of the semiconductor substrate. The solid-state imaging device further includes a photoelectric conversion region including the first conductive region located on the upper surface side of the first conductive region of the semiconductor substrate and the second conductive region and a transfer transistor transferring charges accumulated in the photoelectric conversion region to a readout region; and a pixel including the photoelectric conversion region and the transfer transistor. The first conductive region, which is included in the photoelectric conversion region, extends to the lower side of a sidewall of a gate electrode of the transfer transistor. ## Claims ### Claim 1 A method of manufacturing a solid-state imaging device, the method comprising the steps of: forming lower first and second conductive-type semiconductor regions on a surface of a substrate, the conductivity of said substrate being opposite to the conductivity of said lower second conductive-type semiconductor region; forming a gate electrode between said lower first and second conductive-type semiconductor regions, the conductivity of said lower first conductive-type semiconductor region being opposite to the conductivity of said lower second conductive-type semiconductor region, wherein said lower first and second conductive-type semiconductor regions and said substrate are insulated from said gate electrode, wherein an upper first conductive-type semiconductor region is on said lower first conductive-type semiconductor region, an upper second conductive-type semiconductor region being on said lower second conductive-type semiconductor region, wherein prior to the step of forming the lower first and second conductive-type semiconductor regions, the method further comprising: forming a dummy electrode on said surface of the substrate, said dummy electrode being between a photoelectric conversion region of a transistor and a readout region of the transistor; and thereafter, depositing a semiconductor layer onto said surface of the substrate, said semiconductor layer becoming said lower first and second conductive-type semiconductor regions, wherein said dummy electrode is between said upper and lower first conductive-type semiconductor regions, said dummy electrode being between said upper and lower second conductive-type semiconductor regions, wherein said upper first conductive-type semiconductor region is insulated from said dummy electrode, said dummy electrode being insulated from said upper second conductive-type semiconductor region, wherein removal of said dummy electrode forms an electrode portion, an electric conductor embedded in said electrode portion becoming said gate electrode. ### Claim 2 (depends on 1) The method of manufacturing a solid-state imaging device according to claim 1, wherein said gate electrode is formed after the step of forming the lower first and second conductive-type semiconductor regions. ### Claim 3 (depends on 1) The method of manufacturing a solid-state imaging device according to claim 1, wherein said lower first and second conductive-type semiconductor regions are selective epitaxially grown. ### Claim 4 (depends on 1) The method of manufacturing a solid-state imaging device according to claim 1, wherein the conductivity of said lower first conductive-type semiconductor region is P-type, the conductivity of said lower second conductive-type semiconductor region being N-type. ### Claim 5 (depends on 1) The method of manufacturing a solid-state imaging device according to claim 1, wherein a sidewall is on said lower first conductive-type semiconductor region, another sidewall being on said lower second conductive-type semiconductor region. ### Claim 6 (depends on 1) The method of manufacturing a solid-state imaging device according to claim 1, wherein said lower first conductive-type semiconductor region is deposited onto a second conductive-type layer in the substrate, the conductivity of said second conductive-type layer being opposite to the conductivity of said substrate. ### Claim 7 (depends on 6) The method of manufacturing a solid-state imaging device according to claim 6, wherein said second conductive-type layer is between said lower first conductive-type semiconductor region and a low concentration layer, an impurity concentration of the low concentration layer being lower than an impurity concentration of the second conductive-type layer. ### Claim 8 (depends on 7) The method of manufacturing a solid-state imaging device according to claim 7, wherein the conductivity of said low concentration layer is the same as the conductivity of said second conductive-type layer. ### Claim 9 (depends on 1) The method of manufacturing a solid-state imaging device according to claim 1, wherein said upper first and second conductive-type semiconductor regions are selective epitaxially grown. ### Claim 10 (depends on 1) The method of manufacturing a solid-state imaging device according to claim 1, wherein said gate electrode is insulated from said upper first and second conductive-type semiconductor regions. ### Claim 11 (depends on 1) The method of manufacturing a solid-state imaging device according to claim 1, wherein an impurity concentration of the upper first conductive-type semiconductor region is higher than an impurity concentration of the lower first conductive-type semiconductor region. ### Claim 12 (depends on 1) The method of manufacturing a solid-state imaging device according to claim 1, wherein an impurity concentration of the upper second conductive-type semiconductor region is higher than an impurity concentration of the lower second conductive-type semiconductor region. ### Claim 13 (depends on 1) The method of manufacturing a solid-state imaging device according to claim 1, wherein the conductivity of said upper first conductive-type semiconductor region is opposite to the conductivity of said upper second conductive-type semiconductor region. ### Claim 14 (depends on 1) The method of manufacturing a solid-state imaging device according to claim 1, wherein said lower first conductive-type semiconductor region is in a readout region of a transistor, said lower first conductive-type semiconductor region being in a photoelectric conversion region of the transistor.