US 8,531,471 B2Granted

Shared virtual memory

AssigneeIntel Corporation

InventorsHu Chen, Ying Gao, Zhou Xiaocheng, Shoumeng Yan, Peinan Zhang, Mohan Rajagopalan, Jesse Fang, Avi Mendelson, Bratin Saha

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Abstract

Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Claims15

Dependent claims

A method providing:

sharing memory semantics between a central processing unit (CPU) and a graphics processing unit (GPU) including allowing pointers to be passed and data structures to be shared as is between the CPU and GPU;
allowing the same data structure stored in shared memory to be accessed by both the GPU and CPU;
determining if the CPU and GPU have different page tables and different virtual to physical memory translations;
in response to different page tables and different virtual to physical memory translations, synchronizing contents of virtual address between the CPU and GPU and contents of different physical addresses;
wherein in response to different page tables and different virtual to physical memory translations, synchronizing the contents of virtual address between the CPU and GPU and the contents of different physical addresses further comprises:
during initialization, mapping a portion of a PCI aperture that is accessible to both the CPU and GPU into the user space of an application and instantiating a user space with a task queue, a message queue, and copy buffers;
for copying pages from the CPU to the GPU, copying pages from the CPU address space into the PCI aperture and having the GPU access the pages from the PCI aperture into its address space;
and
for copying pages from the GPU to the CPU, copying pages from the GPU address space into the PCI aperture and having the CPU access the pages from the PCI aperture into its address space.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/317,853Filed 30 Dec 2008 · us provisional application
Priority: 13 Nov 2008
Published: US 2010/0118041 A113 May 2010
Granted: 10 Sep 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

G06T 1/20
General purpose image data processing: processor architectures; Processor configuration, e.g. pipelining
G06F 9/544
Interprogram communication: buffers; Shared memory; Pipes
G06F 12/0815
Multiuser, multiprocessor or multiprocessing cache systems: cache consistency protocols
G06F 12/1036
Using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]: for multiple virtual address spaces,…