Selective management controller authenticated access control to host mapped resources

An information handling system comprising:

• a host mapped general purpose input output (GPIO) including a plurality of registers, wherein a first register includes a system service tag associated with the information handling system;
• a shared memory;
• a host processor in communication with the host mapped GPIO and with the shared memory, the host processor including a basic input output system;
• a board management controller separate from the host processor and in communication with the host mapped GPIO and with the shared memory, the board management controller configured to operate as a proxy for the basic input output system, and to change an input/output state of one of the plurality of registers of the host mapped GPIO based on a state change request and to write data to the shared memory based on a write request received from the basic input output system and when a private key from the basic input output system is authenticated, wherein the private key is based on the system service tag;
• and
• a cryptography engine in communication with the board management controller, the cryptography engine configured to authenticate the private key received from the board management controller.

A method comprising:

• detecting, at a host processor of an information handling system, at least one of an end of a power-on self-test and completion of a runtime write;
• setting, by a board management controller of the information handling system, a host mapped general purpose input output (GPIO) register in a locked state in response to the end of the power-on self-test or to the completion of the runtime write, wherein the GPIO register includes a system service tag associated with the information handling system, and wherein the board management controller is separate from the host processor;
• setting, by the board management controller, a shared memory to a write protected state in response to the end of the power-on self-test or to the completion of the runtime write;
• receiving a first request to change an input/output state of the host mapped GPIO register, or a second request to write to the shared memory;
• receiving, at the board management controller, a private key with the first request or with the second request, wherein the private key is received from a basic input output system of the host processor and is generated based upon the system service tag;
• passing the private key to a cryptography engine;
• receiving an indication that the private key is authenticated from the cryptography engine;
• setting, by the board management controller, the host mapped GPIO register to an unlock state when the private key is authenticated;
• and
• setting, by the board management controller, the shared memory to a full read and write accessible state when the private key is authenticated.