Layout technique for stress management cells

A method, comprising:

• selecting, by a device design system, a first non-functional cell from a plurality of non-functional cells based on a plurality of setup times and the plurality of hold times associated with a set of functional cells for an integrated circuit device, and upon a behavioral characteristic of a functional cell;
• and
• placing, by the device design system, the first non-functional cell at a device layout for the integrated circuit device based on the plurality of setup times and the plurality of hold times associated with the set of functional cells, wherein the placement of the first non-functional cell at the device layout is in a relationship to the functional cell such that the behavioral characteristic of the functional cell is improved;
• wherein:
• placing the first non-functional cell further comprises placing a plurality of non-functional cells to surround the functional cell, the plurality of non-functional cells comprising the first non-functional cell and a third non-functional cell having a common design with the first non-functional cell, wherein each of the plurality of non-functional cells having a different charge carrier mobility;
• the functional cell comprises a logic cell;
• and
• the first non-functional cell and the third non-functional cell do not perform designated logic operations for the data processing device.

A non-transitory computer readable medium tangibly embodying a set of instructions to manipulate a processor to determine a layout of a data processing device design by:

• selecting a first cell based on a charge carrier mobility of the first cell and a behavioral characteristic of the second cell;
• and
• placing the first cell in a relationship to a second cell of the data processing device, wherein in response to placing the first cell in the relationship with the second cell, the behavioral characteristic of the second cell is improved;
• wherein:
• placing the first cell further comprises placing a plurality of cells to surround the second cell, the plurality of cells comprising the first cell and a third cell having a common design with the first cell, wherein each of the plurality of cells having a different charge carrier mobility;
• the second cell comprises a logic cell;
• and
• the first cell and the third cell do not perform designated logic operations for the data processing device.