Automated synthesis of high-performance two operand binary parallel prefix adder

A computer readable non-transitory storage medium comprising a computer readable program for automated synthesis of a two operand binary parallel prefix adder, wherein the computer readable program when executed on a computer causes the computer to perform the steps of:

• determining structural constraints for a given adder device input from a computer storage media;
• generating a plurality of candidate prefix graphs for the adder device by performing a search of possible prefix graphs meeting the constraints by generating a set of n-bit prefix graph solutions P(i), where i is a counter, from each graph in P(n−1) using a recursive method until i=n is reached;
• performing physical synthesis of each of the plurality of candidate prefix graphs to generate performance information for each candidate prefix graph;
• determining one or more of the plurality of candidate prefix graphs that meet performance criteria for incorporation into the adder device;
• and
• if the performance criteria is not met, modifying a prefix graph structure to improve the performance.