Dissection splitting with optical proximity correction to reduce corner rounding

An integrated circuit (IC) method comprising:

• receiving an IC design layout having a main feature, the main feature including first and second corners and an edge spanning between the first and second corners;
• performing a dissection to the edge of the main feature, thereby generating a center segment, a first corner segment, and a second corner segment;
• assigning a first corner target, a second corner target, and a center target to the first corner segment, the second corner segment, and the center segment of the main feature, respectively;
• after assigning the targets, performing a plurality of sequential optical proximity correction (OPC) processes to the IC design layout;
• wherein the performing the plurality of sequential OPC processes includes providing the IC design layout in a format accessible by a mask making tool and wherein the plurality of sequential OPC processes includes a first OPC process for the center target and not the first and second corner targets, and thereafter, a second OPC process for the first and second corner targets and not the center target.

An integrated circuit (IC) design method comprising:

• receiving an IC design layout having a main feature;
• performing a first dissection to the main feature, defining an edge of the main feature, wherein the edge ends at two corners of the main feature;
• performing a second dissection to the defined edge of the main feature, splitting the defined edge into a first corner segment, a second corner segment, and a center segment that is disposed between the first and second corner segments;
• assigning a first corner target, a second corner target, and a center target to the first corner segment, the second corner segment, and the center segment of the main feature, respectively, wherein the first and second corner targets are disposed at an intersection of the defined edge and a respective adjacent edge of the main feature;
• and
• performing an optical proximity correction (OPC) process to the IC design layout, wherein the OPC process includes:
• performing a first OPC sub-process to the main feature for the center target;
• thereafter, performing a second OPC sub-process to the main feature for the first and second corner targets;
• and
• thereafter, performing a third OPC sub-process to the main feature for the center target;
• and wherein the performing the OPC includes providing the IC design layout in a format accessible by a mask making tool.