Method and system for modifying doped region design layout during mask preparation to tune device performance
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMei-Hsuan Lin, Ling-Sung Wang, Chih-Hsun Lin, Chih-Kang Chao
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Abstract
The present disclosure provides a method and system for modifying a doped region design layout during mask preparation to tune device performance. An exemplary method includes receiving an integrated circuit design layout designed to define an integrated circuit, wherein the integrated circuit design layout includes a doped feature layout; identifying an area of the integrated circuit for device performance modification, and modifying a portion of the doped feature layout that corresponds with the identified area of the integrated circuit during a mask preparation process, thereby providing a modified doped feature layout.
Claims14
A method comprising:
- receiving an integrated circuit design layout designed to define an integrated circuit, wherein the integrated circuit design layout includes a doped feature layout;
- identifying, by using a computer, an area of the integrated circuit that includes the doped feature layout for device performance modification, and
- modifying a portion of the doped feature layout that corresponds with the identified area of the integrated circuit during a mask preparation process, thereby providing a modified doped feature layout, wherein the portion of the doped feature layout defines a critical dimension of a resist layer used to form a doped region of the integrated circuit;
- wherein the modifying the portion of the doped feature layout that corresponds with the identified area of the integrated circuit is performed during an optical proximity correction process of the mask preparation process and modifying the portion of the doped feature layout includes modifying to reducing the critical dimension;
- wherein the identifying the area of the integrated circuit for device performance modification includes identifying a transistor for reducing a leakage current;
- and
- forming a doped region in a substrate of the integrated circuit using the mask fabricated according to the modified doped feature layout.
A method comprising:
- receiving a doped feature design layout that defines a critical dimension of a resist layer used to form a doped region of an integrated circuit device;
- modifying, by using a computer, the doped feature design layout during a mask preparation process to adjust performance of the integrated circuit device, wherein the modifying the portion of the doped feature layout that corresponds with the identified area of the integrated circuit is performed during an optical proximity correction process of the mask preparation process, and the modifying includes modifying to reduce the critical dimension;
- wherein the identifying the area of the integrated circuit for device performance modification includes identifying a transistor for reducing a leakage current;
- and
- fabricating a mask according to the modified doped feature design layout.
A system for manufacturing an integrated circuit device, the system comprising:
- a mask making entity operable to fabricate a mask, wherein the mask making entity includes a non-transitory computer readable medium that stores a plurality of instructions for execution by at least one computer processor, wherein the instructions are for:
- receiving a doped feature design layout that defines a critical dimension of a resist layer used to form a doped region of an integrated circuit device, modifying the doped feature design layout during a mask preparation process to adjust performance of the integrated circuit device, wherein the modifying the portion of the doped feature layout that corresponds with the identified area of the integrated circuit is performed during an optical proximity correction process of the mask preparation process and
- modifying the doped feature design layout to adjust performance of the integrated circuit device, wherein the modifying includes modifying to reduce the critical dimension
- wherein the identifying the area of the integrated circuit for device performance modification includes identifying a transistor for reducing a leakage current, and
- fabricating a mask according to the modified doped feature design layout.
Dependencies are inferred from the claim text.