Parity-check-code decoder and receiving system

A receiving system adapted to receive through a channel at least N modulated data that are encoded through parity-check (PC) coding, the receiving system comprising:

• a channel estimator to estimate a channel quality ratio of a channel receiving quality based on the modulated data;
• and
• a PC code decoder, coupled to said channel estimator, to obtain at least N bit nodes based on the modulated data, said PC code decoder including a verifying circuit, a reliability-generating circuit, a bit-exchange circuit, a check-exchange circuit, and a reliability-updating circuit,
• wherein said bit-exchange circuit includes a multiplying unit and a first subtraction unit.

A receiving system adapted to receive through a channel at least N modulated data that are encoded through parity-check (PC) coding, the receiving system comprising:

• a channel estimator to estimate a channel quality ratio of a channel receiving quality based on the modulated data:
• and
• a PC code decoder, coupled to said channel estimator, to obtain at least N bit nodes based on the modulated data, said PC code decoder including a verifying circuit, a reliability-generating circuit, a bit-exchange circuit, a check-exchange circuit, and a reliability-updating circuit,
• wherein said bit-exchange circuit includes a sign determining unit, a minimum value selecting unit, and a multiplexer unit.

A parity-check (PC) code decoder adapted for receiving a channel quality ratio of a channel receiving quality and at least N bits that are encoded in a PC code, each of the at least N bits being as a bit node, said decoder comprising:

• a verifying circuit to obtain N-K check nodes according to the N bit nodes and a PC code matrix, each of the check nodes exchanging messages with at least two of the bit nodes;
• a reliability-generating circuit to generate a reliability index for each of the bit nodes;
• a bit-exchange circuit, coupled to said reliability-generating circuit, to generate at least two extrinsic bit indices for each of the check nodes based on the channel quality ratio and the extrinsic check indices, wherein the bit-exchange comprises a multiplexer unit configured to output each of the at least two extrinsic bit indices based on a sign index generated according to the extrinsic check indices;
• a check-exchange circuit, coupled to said bit-exchange circuit, to update a plurality of the extrinsic check indices based on the extrinsic bit indices, and provide the extrinsic check indices to the bit nodes;
• and
• a reliability-updating circuit, coupled to said check-exchange circuit and said verifying circuit, to update the reliability index of each of the bit nodes based on the extrinsic check indices, and determine an updated value for each of the bit nodes.