System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errors

A communication system comprising:

• an encoder, comprising:
• a plurality of register blocks;
• a plurality of adder logic blocks, said plurality of adder logic blocks being communicatively coupled with the plurality of register blocks;
• a switching logic block, said switching logic block being communicatively coupled with the plurality of adder logic blocks, said switching logic block being configured for receiving a plurality of information bits of an information word received by the encoder, said switching logic block further configured for generating a first output based on a first set of information bits included in the plurality of information bits, said switching logic block further configured for generating a second output based on a second set of information bits included in the plurality of information bits, said switching logic block further configured for providing the second output to the plurality of adder logic blocks;
• and
• a universal multipole block having n inputs and 22n outputs, said universal multipole block being communicatively coupled with the plurality of adder logic blocks, said universal multipole block being configured for receiving an error number input, said universal multipole block further configured for calculating a plurality of error coefficients based on the error number input, said universal multipole block further configured for outputting the plurality of coefficients to the adder logic blocks, said universal mulitpole configured to implement Boolean functions on said n inputs,
• wherein the adder logic blocks are configured for calculating a plurality of parity bits based on the error coefficients received from the universal multipole block and further based on the second output received from the switching logic block, said adder logic blocks further configured for providing the parity bits to the plurality of register blocks, the encoder configured for outputting the parity bits and the first output of the switching logic block;
• and
• a decoder, comprising:
• a plurality of register blocks;
• a plurality of adder logic blocks, said plurality of adder logic blocks being communicatively coupled with the plurality of register blocks;
• a universal multipole block having 22n inputs and n outputs, said universal multipole block being communicatively coupled with the plurality of adder logic blocks, said universal multipole block being configured for receiving a plurality of encoded information bits, said universal multipole block further configured for calculating a plurality of error coefficients based on the encoded information bits, said universal multipole block further configured for outputting the plurality of error coefficients to the adder logic blocks, said universal mulitpole configured to implement Boolean functions on said n inputs;
• and
• a switching logic block, said switching logic block being communicatively coupled with the plurality of adder logic blocks, said switching logic block being configured for receiving a plurality of encoded information bits of an encoded information word received by the decoder, said switching logic block further configured for generating a first output based on a first set of encoded information bits included in the plurality of encoded information bits, said switching logic block further configured for generating a second output based on a second set of encoded information bits included in the plurality of encoded information bits, said switching logic block further configured for providing the second output to the plurality of adder logic blocks,
• wherein the adder logic blocks are configured for decoding an encoded information word having a plurality of parity bits based on the error coefficients received from the universal multipole block and further based on the second output received from the switching logic block, said adder logic blocks further configured for providing the decoded information word to the plurality of register blocks, the decoder configured for outputting the decoded information word.

A decoder, comprising:

• a plurality of register blocks;
• a plurality of adder logic blocks, said plurality of adder logic blocks being communicatively coupled with the plurality of register blocks;
• a universal multipole block having 22n inputs and n outputs, said universal multipole block being communicatively coupled with the plurality of adder logic blocks, said universal mulitpole configured to implement Boolean functions on said n inputs;
• and
• a switching logic block, said switching logic block being communicatively coupled with the plurality of adder logic blocks, said switching logic block being configured for receiving a plurality of encoded information bits of an encoded information word received by the decoder,
• wherein the decoder is configured to decode data according to binary Bose-Chaudhuri-Hocquenghem codes.