High speed hard LDPC decoder
AssigneeSTEC, Inc.
InventorsLevente Peter Jakab, Dillip K. Dash
Life of this patent
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Abstract
The subject disclosure describes a method for performing error code correction, the method includes, loading a code word including a plurality of encoded bits into a memory array, initializing, into one or more of a plurality of memory units, a plurality of bits associated with each of the encoded bits, wherein the plurality of bits initialized for each of the encoded bits is based on a value of the associated encoded bit and wherein the plurality of encoded bits and the plurality of bits initialized for each of the encoded bits includes soft information. In certain aspects, the method further includes decoding the code word using the soft information and outputting the decoded code word from the memory array. A decoder and flash storage device are also provided.
Claims18
A computer-implemented method for performing code word decoding, the method comprising:
- loading a code word comprising a plurality of encoded bits into a memory array;
- initializing, into one or more of a plurality of memory units, a plurality of bits associated with each of the encoded bits, wherein the plurality of bits initialized for each of the encoded bits is based on a value of the associated encoded bit and wherein the plurality of encoded bits and the plurality of bits initialized for each of the encoded bits comprises soft information;
- decoding the code word using the soft information;
- and
- outputting the decoded code word from the memory array, without outputting the plurality of bits from the plurality of memory units.
A decoder for performing error correction on payload data, the decoder comprising:
- a top bit array configured to store a code word comprising a plurality of encoded bits;
- a plurality of memory units configured to store a plurality of bits initialized for each of the encoded bits;
- and
- a plurality of processing units, wherein each of the processing units is coupled to the top bit array and to at least one of the plurality of memory units, and
- wherein the plurality of processing units are configured to decode the code word using soft information comprising the plurality of encoded bits and the plurality of bits initialized for each of the encoded bits.
A flash storage device, comprising:
- a flash memory array;
- a controller;
- and
- a decoder coupled to the flash memory array and the controller, the decoder further comprising:
- a top bit array configured to store a code word comprising a plurality of encoded bits;
- a plurality of memory units configured to store a plurality of bits initialized for each of the encoded bits;
- and
- a plurality of processing units, wherein each of the plurality of processing units is coupled to the top bit array and to at least one of the plurality of memory units, and
- wherein each of the processing units is configured to decode the code word using soft information comprising the plurality of encoded bits and the plurality of bits initialized for each of the encoded bits.
Dependencies are inferred from the claim text.