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US 8,527,836 B2Granted
Rank-specific cyclic redundancy check
AssigneeIntel Corporation
InventorsRamesh Subashchandrabose, Tessil Thomas, Sambaran Mitra, Debaleena Das, Kai Cheng
Life of this patent
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Abstract
Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.
Claims21
An apparatus comprising:
- a cyclic redundancy check (CRC) enabler configured to receive an indication of a CRC-trigger condition with respect to a first rank of a plurality of ranks of a memory module, and to generate a CRC enable signal based on receipt of the indication;
- and
- a plurality of timing components coupled with the CRC enabler, each timing component of the plurality of timing components to a rank of the plurality of ranks, wherein a first timing component of the plurality of timing components that corresponds to the first rank of the plurality of ranks is configured to generate a command blackout control to accommodate CRC for the first rank based on receipt of the CRC enable signal.
A method comprising:
- detecting a cyclic redundancy check trigger condition for a first rank of a plurality of ranks of a memory module;
- dynamically enabling CRC processes for memory commands issued to the first rank based on said detecting;
- and
- dynamically enabling CRC timing for ranks of the plurality of ranks that share a memory channel with the first rank.
1 more element
One or more non-transitory computer readable media comprising instructions to, upon execution of the instructions by a computing device, cause the computing device to:
- detect a cyclic redundancy check trigger condition for a first rank of a plurality of ranks of a memory module;
- dynamically enable CRC processes for memory commands issued to the first rank based on said detecting;
- and
- dynamically enable CRC timing for ranks of the plurality of ranks that share a memory channel with the first rank.
1 more element
Dependencies are inferred from the claim text.