Testing of multi-clock domains
AssigneeSTMicroelectronics International N.V.
InventorsSwapnil Bahl, Akhil Garg
Life of this patent
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Abstract
A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.
Claims5
A method for testing an integrated circuit (IC), the method comprising:
- providing, based on a scan enable signal, capture pulses at a frequency of a first fast clock to a first clock domain of the IC;
- delaying the scan enable signal by at least a time duration of the capture pulses at the frequency of the first fast clock;
- and
- providing, based on the delaying, capture pulses at a frequency of a second fast clock to a second clock domain of the IC.
Dependencies are inferred from the claim text.