Gating of clock-DR and pause-DR from TAP to TCA

An electrical device comprising:

• A. a test data in lead, a test clock lead, a test mode select lead, and a test data out lead;
• B. a test access port including a test data in input coupled to the test data in lead, a test clock input coupled to the test clock lead, a test mode select input coupled to the test mode select lead, a test data out output coupled to the test data out lead, a scan data input, a scan clock output, and a scan enable output, the test access port including:
• i. a state machine circuitry having inputs coupled to the test clock input and the test mode select input and having a Clock-DR signal output and a Pause-DR state output;
• ii. an instruction register having a serial input coupled to the test data in input and having control outputs;
• and
• iii. gating circuitry having inputs connected to the test clock input, the Clock-DR signal output, the Pause-DR state output, and the control outputs of the instruction register, and having outputs connected to the scan clock output and the scan enable output;
• and
• C. a test compression architecture circuit having a compressed data input coupled to the test data in lead, a compressed data output coupled to the scan data input of the test access port, a scan clock input coupled to the scan clock output from the test access port, and a scan enable input coupled to the scan enable output from the test access port.