System and method for single terminal boundary scan
AssigneeNXP B.V.
InventorsHenk Boezen, Leon Van de Logt, Liquan Fang
Life of this patent
Estimating the term…
Abstract
An electronic circuit having a boundary scan test circuit receives, though one pin, an embedded clock encoded test signal having an encoded bit stream having occurrences of a first header followed by at least one encoded boundary scan mode bit and an encoded second header followed by at least one boundary scan test input bit. The bit stream and the clock are extracted and occurrences of the first header and second header are detected. Based on the detected occurrences the boundary scan mode bits and boundary scan input bits are identified and distributed to the electronic circuit, along with the extracted clock, and boundary scan test is performed.
Claims19
A testable electronic circuit connected to a terminal, comprising:
- an embedded clock boundary scan test decoder connected to said terminal, configured to receive a given embedded clock encoded signal having encoded test information bits, generate a test clock signal based on the received signal, detect the encoded test information bits and, in response to the detected test information bits matching a given preamble sequence, generate a sequence of test state control bits based on a subsequently received sequence of the encoded test information bits;
- and
- an electronic function circuit connected to said terminal, wherein said electronic function circuit is switchable, in response to the generated sequence of the test state control bits, between an operational mode and a test mode, and configured to perform, in the test mode, a test operation in accordance with the generated sequence of the test state control bits and the generated test clock signal, and output a corresponding test output data signal.
A method for performing JTAG boundary scan testing of an electronic circuit connected to a terminal, the electronic circuit having a JTAG boundary scan test circuit to distribute JTAG Test Mode Select (TMS) bits and JTAG Test Data Input (TDI) bits to selectable portions of the electronic circuit and to detect states of the electronic circuit in relation to the TMS and TDI bits, the method comprising:
- generating an embedded clock encoded signal having an encoded first header followed by at least one encoded TMS bit and an encoded second header followed by at least one TDI bit;
- receiving said generated clock encoded signal at said terminal;
- extracting test bits and a test clock from said received clock encoded signal;
- detecting an occurrence of said encoded first header in said extracted test bits and, in response, generating a sequence of at least one TMS bit based on the at least one TMS bit following said detected occurrence;
- detecting an occurrence of said encoded second header in said extracted test bits and, in response, generating a sequence of at least one TDI bit based on the at least one TDI bit following said detected occurrence;
- and
- performing a JTAG boundary scan test in accordance with said generated TMS bits, said generated TDI bits, and said extracted test clock.
A method for testing an electronic circuit connected to a terminal, the electronic circuit having a boundary scan test circuit to distribute given test bits to a selectable portion of the electronic circuit and to distribute given circuit test mode select bits to a selectable portion of the electronic circuit, to detect states of the electronic circuit in relation to the given test bits and the given circuit test mode select bits, and to output corresponding state data, the method comprising:
- receiving a given embedded clock encoded signal at said terminal, said received clock encoded signal having encoded test information bits;
- extracting a recovered clock signal and said test information bits from said received clock encoded signal;
- detecting a characteristic of the received clock encoded signal and generating a timeout signal if said received clock encoded signal fails to meet said characteristic for a given duration;
- generating a sequence of one or more of the circuit test mode select bits in response to detecting a sequence of the test information bits meeting a given first preamble sequence and input, said generating continuing until receiving said timeout signal;
- generating a sequence of one or more of circuit test data bits in response to detecting a sequence of the test information bits meeting a given second preamble sequence, said generating continuing until receiving said timeout signal;
- and
- performing test operations on the electronic circuit in accordance with the circuit test mode select bits, the circuit test data bits, and the recovered clock signal;
- and
- outputting a corresponding test output data signal.
Dependencies are inferred from the claim text.