Hybrid test compression architecture using multiple codecs for low pin count and high compression devices

An integrated circuit comprising:

• at least one scan input;
• a decompressor including
• a plurality of decompression codecs, each decompression codec having an input connected to said at least one scan input and an output generating decompressed data according to a codec parameter different from a codec parameter of every other of the plurality of decompression codecs, said plurality of decompression codecs include a first decompression codec having as said codec parameter a combinational codec and a second decompression codec having as said codec a sequential codec;
• an operational circuit having a plurality of serial scan chains, each serial chain having inputs connected to a selected of one said plurality of decompression codecs and outputs;
• a compressor including
• a plurality of compression codecs, each compression codec having an input connected to said output of said plurality of serial scan chain and an output generating compressed data according to a codec parameter different from said codec parameter of every other of the plurality of compression codecs;
• at least one scan output outputting data from a selected one of said plurality of compression codecs.

A method of testing an integrated circuit comprising the steps of:

• scanning test data into the integrated circuit via scan inputs;
• a plurality of iterations of
• decompressing the test data into decompressed data employing corresponding unique decompression codec parameters,
• scanning decompressed data into inputs of plural serial scan chains in the integrated circuit,
• running the integrated circuit for a predetermined number of machine cycles,
• scanning data out of outputs of the plural serial scan chains,
• compressing scanned out data into compressed scanned out data employing unique compression codec parameters,
• comparing the compressed scanned out data to a corresponding standard;
• said plurality of iterations comprises two iterations including
• a first iteration wherein the decompression codec has as said codec parameter a first fault tolerance and the compression codec has as said codec parameter a corresponding first fault tolerance, and
• a second iteration wherein the decompression codec has as said codec parameter a second fault tolerance lower than the first fault tolerance and the compression codec has as said codec parameter a corresponding second fault tolerance lower than the first fault tolerance;
• and
• stopping testing if said compressed scanned out data does not match said corresponding standard.

A method of testing an integrated circuit comprising the steps of:

• scanning test data into the integrated circuit via scan inputs;
• a plurality of iterations of
• decompressing the test data into decompressed data employing corresponding unique decompression codec parameters,
• scanning decompressed data into inputs of plural serial scan chains in the integrated circuit,
• running the integrated circuit for a predetermined number of machine cycles,
• scanning data out of outputs of the plural serial scan chains,
• compressing scanned out data into compressed scanned out data employing unique compression codec parameters,
• comparing the compressed scanned out data to a corresponding standard;
• said plurality of iterations comprises two iterations including
• a first iteration wherein the decompression codec has as said codec parameter a combinational codec and the compression codec has as said codec parameter a corresponding combinational codec, and
• a second iteration wherein the decompression codec has as said codec parameter a sequential codec and the compression codec has as said codec parameter a corresponding sequential codec;
• and
• stopping testing if said compressed scanned out data does not match said corresponding standard.