Information processing device
AssigneeRenesas Electronics Corporation
InventorTakahiro Shiina
Life of this patent
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AssigneeRenesas Electronics Corporation
InventorTakahiro Shiina
Estimating the term…
The invented device includes a central processing unit(s), each CPU including an execution unit coupled to an operand bus and a control unit that controls operation of the execution unit, based on fetched instructions, and a debugging circuit that obtains trace data about how a program is executed in each CPU. The control unit includes a debugging function unit that collects instruction execution analysis data in the CPU. The debugging circuit includes a trace acquisition circuit(s) that imports instruction execution analysis data collected by the debugging function unit and data received from the operand bus via logic circuits used for separate purposes and a trace output circuit(s) for delivering outside the output of the trace acquisition circuit. In the trace acquisition circuit, a sorting logic unit is provided that sorts instruction execution analysis data collected by the debugging function unit and data received from the operand bus.
An information processing device comprising:
Dependencies are inferred from the claim text.